Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell



It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU statement can locate a strike anywhere in the semiconductor and at any time during the transient, offering a range of simulation possibilities. One possible use for simulating multiple SEU strikes is for simulating spallation events, where a high energy particle, such as a cosmic ray, suffers a nuclear interaction, producing one or more different sources of ionizing particle at the nuclear reaction site. In this article, we will, demonstrate two SEU strikes in different locations at two different times on a full six transistor 22nm SRAM cell, including four layers of metal interconnect.


Simulation Set Up

A standard six transistor SRAM cell layout was created in MaskViews, with the major lower layers shown in Figure 1. As can be seen from Figure 1, the entire SRAM cell measures only 0.35um x 0.2um. Next a 22nm process flow was developed for both nMOS and pMOS transistors and simulated using Victory Process (Cell Mode). Monte-Carlo implantation was used throughout in the interests of creating realistic doping profiles, typically simulating 40 million ions per implant.


Figure 1. Basic lower layers of the SRAM designed using MaskViews.


The full 3D process simulated SRAM cell, including all relevant interconnect, is shown in Figure 2 with the insulating layers removed for clarity. The design of the layout and process flow allowed satisfactory operation at a power supply line voltage of just 0.8 volts.

Figure 2. Full 3D process simulated structure of the six transistor 22nm SRAM cell, including interconnect, showing absolute net doping.


The first task when simulating a cell’s sensitivity to a single event upset (SEU) event is to locate sensitive areas of the circuit that will be especially sensitive to a transistor transitioning from an off state to an on state, since an SEU strike effectively forces a transistor into a conducting state, whether it was previously conducting or not. It is also intuitively clear that since an SRAM circuit is geometrically symmetrical, it is not possible in advance to predict the SRAM cell’s logical output state on power-up. Thus which of the individual transistors in the SRAM cell are in the off state and are therefore most sensitive to an SEU strike, is also not known in advance.

To solve the issue of not knowing which transistors are conducting on power up and which are not, two SEU strikes were applied with a staggered time interval in between the two strikes. Each nMOS transistor in the active flip flop, were struck in the central channel region in turn, with the staggered time interval between strikes being long enough, such that a circuit recovery or a logic state flip, would be established before the next strike occurred. With this sequence, at least one logic flipped state could be guaranteed, as shown in the truth table below, which represents an SEU powerful enough to always flip the state of the flip flop, if it hits the channel of the off state transistor. Remember, if the truth table initially looks confusing, that if the off state transistor is flipped, then the other previously on transistor will be forced to it’s off state, such that transistors nMOS1 and nMOS2 in the flip flop truth table are always eventually forced into opposite states.

Following the truth table, we can see that the flip flop will either change state once or twice depending on whether the first strike hits a transistor in the off state or the on state.

Previous State
MOS 1 Strike
MOS 2 Strike
nMOS 1
nMOS 2
Table 1. Truth table for flip flop states after an SEU strike.



Simulation Results

The entire simulation sequence was run in transient mode, including the initial ramp up of the power supply. The power supply was ramped up to 0.8 volts in 1 nano second, and then left to stabilize for a further 1 nano second. This ramp up sequence provided the plot of supply voltage versus the SRAM output states Q and Q_bar, as shown in Figure 3. The output states of Q and Q_bar started to separate to their opposite states at approximately half the supply voltage, showing that a supply voltage of 0.8 volts provided ample positive feedback for the flip flop to work adequately.

Figure 3. Power on Output Characteristics of the SRAM Cell.


The second part of the transient, simulated the two SEU strikes, 2 nano seconds apart. Two nano seconds proved to be sufficient time for the SRAM to either recover or suffer an output state flip, depending on whether the SEU strike hit a transistor in the “on” state or in the “off” state respectively.

The SEU strikes were defined with a radius of 25 nano meters and a pulse width of 1 pico second and were located in the channel region of the transistors “M1” and “M3” in the schematic diagram shown in Figure 4. Figure 5 shows what happens when the “off” state nMOS gets struck first. In this case, the struck transistor momentarily conducts more than it’s complementary pMOS, pulling down the output voltage at that node, which flips the memory state of the SRAM. This results in the other nMOS transistor, that was previously in the “on” state, being transferred into the “off” state. Now when this transistor, now in an off state, is hit with the secondary SEU strike, the SRAM cell output flips once again.

Figure 4. Schematic Showing Location of the Two SEU Strikes at M1 and M3.


Figure 5. SRAM Output when the First Strike Occurs on the “Off” state nMOS.


Figure 6 shows what happens if the transistor that gets struck first was in a conducting (“on”) state. Since the transistor was already conducting, making it conduct even more, has little effect on the output of the SRAM cell, except for a voltage transient which momentarily pulls down the output, from which it quickly recovers. Since the SRAM did not change state, the other nMOS must be in the “off” state, so when this transistor gets hit with the second SEU strike, the SRAM cell flips state as expected.

Figure 6. SRAM Output when the First Strike Occurs on the “On” state nMOS.



We have demonstrated dual Single Event Upset (SEU) strikes at different locations and at different times on a 22nm six transistor SRAM cell structure created in Victory Process (Cell Mode), and using the Victory Device Simulator for the transient device simulations.