Anode Shorts Layout Dependence of Bi-mode IGBT (BiGT) On-state Characteristics


Reverse Conducting IGBT (RC-IGBT)

A new class of high-voltage semiconductor devices, known as a reverse conducting IGBT (RC-IGBT), has emerged in recent years from research efforts to diminish the usage of external anti-parallel free-wheeling diode chips for IGBT switching applications. The RC-IGBT device concept is based on the monolithic integration of a freewheeling diode into an IGBT chip. Hereby, an anti-parallel diode is formed through the embedment of an n+ region in an anode/collector region of the IGBT. Both the n+ region and the p+ anode are then shorted together by an anode/collector contact. Although the RC-IGBT has many advantages over the conventional IGBT, especially in terms of manufacturing cost, total chip size and reliability of power modules, it is detrimental to the snapback effect at forward conduction of IGBT mode.


Snapback Effect in RC-IGBT

In the on-state IGBT mode of an RC-IGBT, when electrons flow from a cathode/emitter contact through an n-buffer region (or an n-drift region in case of a non-punch-through IGBT) to an n+ region at the anode/collector contact, they forward bias the p+-anode /n-buffer junction. On grounds of reflection symmetry, the voltage drop across the junction has its maximum value in the middle of the p+ anode region. Only after a sufficiently high voltage drop has built up in response to an increase in the collector current does the p+ anode start injecting holes into the n- drain drift region, with the result that the drift region becomes less resistive by conductivity modulation. An increase in hole levels in the drift region above the doping concentration eventually gives rise to a voltage snapback.


Bi-mode Insulated Gate Transistor (BiGT)

The Bi-mode insulated gate transistor (BiGT) represents a further development of the RC-IGBT device concept, with the primary objective of alleviating the snapback effect in RC-IGBT. Recent research results have indicated that the snapback voltage in the RC-IGBT on-state characteristics decreases with the increase of the width of the p+ anode [1]. Accordingly, the BiGT device is built around the concept of incorporating an IGBT with a wide p+ anode, also referred to as pilot-IGBT, into the RC-IGBT structure as outlined in Figure 1.

Figure 1. The basic structure of a BiGT [2].


Design Analysis and 3D Simulation with Victory Process and Device

Studies in [3] have shown that, in the on-state of the BiGT, the anode shorts layout design of the RC-IGBT portion affects the conductivity modulation of the entire BiGT, and therefore its on-state behavior. They attribute the cause of this layout-dependent device performance to the lateral spread of the electron-hole plasma from the pilot-IGBT into the RC-IGBT and suggest a possibility of snapback suppression by a radial layout design of anode shorts.

In order to verify the validity of the arguments and reproduce the results reported in [3], 3D device simulations with Victory Device have been performed in combination with process simulation with Victory Process. Figure 2 illustrates the simulation structure of the BiGT as well as the anode shorts layout designs under consideration.


Figure 2. BiGT device for use in 3D simulation: (a) Cross sectional representation of the structure (b) Anode shorts layout designs.


It follows that there are two basic patterns for anode shorts layouts – stripes (designs S1, S2 and S3), with each having the same width of 100 µm but different orientations relative to the pilot-IGBT boundary, and square dots (designs D1 and D2), with each having squares whose all four sides equal to 100 µm and 224 µm respectively.

In the simulation domain with an area of 0.5 mm × 4 mm, the BiGT assumes a 100 µm-thick drain drift region, together with a 10 µm-thick SPT n+ buffer layer on a 2.5 µm-thick anode/collector region. For simplicity, the MOS cells on the emitter side are modeled with a 1 µm-thick heavily doped n-type layer of silicon, given the conducting state of the BiGT in the IGBT mode.


Simulation Results

Based on a transient simulation technique, in which the collector current is ramped from 0 A to 24 A at a constant rate over a period of time, Victory Device captures a number of small secondary snapbacks in simulated I-V characteristics in IGBT mode of design S1 and a large snapback in design S3 (Figure 3). On the other hand, there is no sign of a voltage snapback in designs S2, D1, and D2 (Figure 5).

Figure 3. Simulated I-V characteristics of the devices with the stripe layout design of anode shorts (S1, S2, S3).


Figure 4. Carrier density distribution in the devices with the stripe layout design of anode shorts (S1, S2, S3), visualized in a cut plane above the anode/collector region.


Figure 5. Simulated I-V characteristics of the devices with the square dots pattern (D1, D2) in comparison to the device with the radial layout design (S2).


During the current ramp-up Victory Device also outputs carrier density data for visual inspection of the detail of carrier expansion with TonyPlot in a cut plane defined along the z-axis at z = -40 µm (Figure 2a). Within the simulation domain comprising an area of 3 mm × 4 mm, the plan view of carrier density distribution in the device with different anode shorts design variants is displayed at specific values of collector current in Figure 4 and Figure 6.

Figure 6. Carrier density distribution in the devices with the square dots pattern (D1, D2) in comparison to the device with the radial layout design (S2), visualized in a cut plane above the anode/collector region.


Analysis of Results

In the case of design S1, injection from each 100 µm-wide anode segment occurs by progressive stages as the electron current flows perpendicularly through the p+ anode segments. This means that injection from each anode segment corresponds to each secondary snapback in the device with design S1.

By contrast, the radial configuration of anode segments in the S2 design enables the electrons from the pilot-IGBT to flow and forward bias the p+ anode/n-buffer junction along the entire stripe length. As a result, the portion of anode segments adjacent to the pilot-IGBT starts injecting carriers that later on spread smoothly and without causing a voltage snapback all over the entire device volume at a relatively low current, compared to the S1 design.

With regard to design S3, the orthogonally arranged anode segments are disconnected to the pilot-IGBT, so hole injection from the anode stripes triggers a voltage snapback at a higher current than design S1. Nevertheless, after the onset of snapback the anode stripes of design S3 rapidly supply the entire device volume with plasma, which thus renders the I-V curve behavior of design S3 at high current levels identical with that of design S2.

As far as the square dots pattern is concerned, the transition of the devices with the D1 and D2 designs into full conduction goes as smoothly as the case of radial layout design S2, except that the available anode segment area essentially determines the device IGBT mode on-state I-V characteristics. Figure 5 reveals that the radial stripe design S2 exhibits a slightly higher on-state voltage drop than the D1 design but incurs almost exactly the same conduction losses as design D2. This agrees well with the fact that the S2 design provides the entire device area with almost exactly the same plasma as design D2, as it can be seen in Figure 6.



Victory Process and Device proves to be capable of reproducing consistent simulation data with reference to [3]. It allows users to speed up the product design process and shorten the development timeline considerably.



  1. M. Rahimo, J. Vobecky, C. Corvasce,“1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology,” Proc. ISPS10, pp. 243-247, 2010.
  2. M. Rahimo, A. Kopta, U. Schlapbach, J. Vobecky, R. Schnell, S. Klaka, “The Bi-mode Insulated Gate Transistor (BiGT) A potential technology for higher power applications,” Proc. ISPSD09, pp. 282-286, 2009.
  3. L. Storasta, M. Rahimo, M. Bellini, A. Kopta, U. R. Vemulapati, and N. Kaminski,“The Radial Layout Design Concept for the Bi-mode Insulated Gate Transistor,” Proc. ISPSD11, pp. 56-59, 2011.

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