Published Papers

Analog, Mixed Signal, RF

The full text of most of these papers may be found at the IEEE website at

Isato Ogawa,Tomoharu Yokoyama,Mutsumi Kimura,
"Simulation of neural network using ferroelectric capacitor,"
IEICE Technical Report Vol.117 No.372, No.373 , Dec 2017

Dondee Navarro*, Takeshi Sano*, and Yoshiharu Furui*,
"A Sequential Model Parameter Extraction Technique for Physics-Based IGBT Compact Models,"
IEEE Transactions on Electron Devices, Vol. 60, Issue 2, pp. 580-586, Feb. 2013.
*Silvaco engineer

Masataka Miyake, Dondee Navarro*, Uwe Feldmann, Hans Juergen Mattausch, Takashi Kojima, Takaoki Ogawa, and Takashi Ueta,
"HiSIM-IGBT: A Compact Si-IGBT Model for Power Electronic Circuit Design",
IEEE Transactions on Electron Devices, Vol. 60, Issue 2, pp. 571 - 579, Feb. 2013.
*Silvaco engineer

Masataka Miyake, Fumiya Ueno, Dondee Navarro*, and Mitiko Miura-Mattausch,
"Compact Modeling of the Punch-Through Effect in SiC-IGBT for 6.6kV Switching Operation with Improved Performance",
Materials Science Forum Vols. 740-742, pp. 1103-1106, Jan. 2013.
*Silvaco engineer

Yoshihisa Iino*,
"HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS
Comparison of the Temperature Flag Options
SILVACO Japan, MIYAKE Bldg. 4F, 549-2 Shinano-cho Totsuka-ku, Yokohama 244-0801, Japan
*Silvaco engineer

Srivatsava Jandhyala, Aby Abraham, Costin Anghel, Member, IEEE, and Santanu Mahapatra, Senior Member, IEEE,
"Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET",

Srivatsava Jandhyala, Rutwick Kashyap, Costin Anghel, Santanu Mahapatra,
"A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry",

Aby Abraham, Srivatsava Jandhyala, and Santanu Mahapatra,
"Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET",

Srivatsava Jandhyala and Santanu Mahapatra,
"An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET",

A. Akturk, M. Peckerar, K. Eng, J. Hamlet, S. Potbhare, E. Longoria, R. Young, T. Gurrieri, M.S. Carroll, N. Goldsman,
"Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A",
Microelectronic Engineering, Vol. 87, Issue 12, December 2010, pp. 2518-2524.

P. Martin, M. Cavelier, R. Fascio, G. Ghibaudo, M. Bucher,
"EKV3 compact modeling of MOS transistors from a 0.18 μm CMOS technology for mixed analog–digital circuit design at low temperature",
Cryogenics, Vol. 49, Issue 11, November 2009, pp. 595-598.

X. -H. Du and B. Sheu
"Modeling ferroelectric capacitors for memory applications"
IEEE Circuits and Devices Magazine, Vol. 18, Issue 6, November 2002, pp. 10-16.

S. Lee, C. S. Kim, H. K. Yu
"Improved BSIM3v3 model for RF MOSFET IC simulation"
Electronics Letters, Vol. 36, Issue 21, 12 October 2000, pp. 1818-1819

Y. Iino (Silvaco Japan)
"A trial report: HiSIM-1.2 parameter extraction for 90 nm technology"
2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004, Vol. 2, 2004 NSTI Nanote

M. N. Marbell, S. V. Cherepko, A. Madjar, J. C. M. Hwang, M. Frei, M. A. Shibib
"An improved large-signal model for harmonic-balance simulation of Si LD-MOSFETs"
Conference Proceedings - European Microwave Conference, Vol. 1, 2004, pp. 225-228.

S.-H. Lee, J. Y. Lee, S. -Y. Lee, C. W. Park, H. -C. Bae, J. -Y. Kang
"VBIC model application and model parameter optimization for sige HBT"
Electrochemical Society Proceedings, Vol. 7, 2004, pp. 385-394. "

W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury
"Low current application dedicated process characterization method"
IEEE International Conference on Microelectronic Test Structures, 2002, pp. 41-44.

S. V. Cherepko, M. S. Shirokov, J. C. M. Hwang, A. Brandstaedter
"Improved large-signal model and model extraction procedure for InGaP/GaAs HBTs under high-current operations"
IEEE MTT-S International Microwave Symposium Digest, Vol. 2, 2001, pp. 671-674."

P. R. Palmer, J. C. Joyce, P. Y. Eng, J. Hudgins, E. Santi, R. Dougal
"Circuit simulator models for the diode and IGBT with full temperature dependent features"
PESC Record - IEEE Annual Power Electronics Specialists Conference, Vol. 4, 2001, pp. 2171-2177

A. A. Keshavarz, J. L. Walters, R. K. Sampson
"Mobility degradation and current loss due to vertical electric field in channel area of submicron MOS devices"
2000 International Conference on Modeling and Simulation of Microsystems - MSM 2000, 2000, pp. 34

Lee S. Kim C.S. Yu H.K.
"Improved SPICE Modelling and Parameter Extraction for RF MOSFETs"
Proc. ESSDERC 2001.

T. Myono, E. Nishibe, S. Kikuchi and et al.,
"Modeling and parameter extraction technique for uni-directional HV MOS devices"
IEICE T. Fund. Electr., Vol. E83A, Mar. 2000, pp. 412-420.

T. Myono, E. Nishibe, S. Kikuchi and et al.,
"High-voltage MOS device modeling with BSIM3v3 SPICE model"
IEICE Trans. Electronics, Vol. E82C, Apr. 1999, pp. 630-637.

Arun N. Lokanathan, Jay B. Brockman
"Process Multi-Circuit Optimization"
Proceedings of the 35th IEEE Conference on Design Automation, 15-19 Jun 1998, pp. 382-387.

Eric Vandenbossche, Georege Kopalidis, Marnix Tack and Wim Schoenmaker
"Statistical Modeling based on extensive TCAD simulations Proposed methodology for extraction of Fast/Slow models and Statistical models"
Proc. SISPAD, 1998, pp. 85-88.

M. A. Imam, M .A. Osman and A. A. Osman,
"MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model"
IEEE Trans. Computer-Aided Design, Vol. 15, Apr. 1996, pp. 446-451.

R. Clancy, M. Welten, J. A. Power, B. Mason, P. Stribley and A. Mathewson
"A comparison of RS/1 and SPAYN for the generation of worst-case SPICE level 3 MOSFET model parameters"
IEE Colloquium on Improving the Efficiency of IC Manufacturing Technology, 1995, pp. 7/1 -7/4.

M.Welten et al
"Enhanced Worst-Case Simulation Utilising Regression based performance spread"
Proc ESSDERC 95, The Hague, Netherlands, pp. 761-764.

J.Power et al
"Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design"
IEEE Trans. on Semiconductor manufacturing, Vol. 7 August 1994, pp. 306-318.

Clancy, Welton, Wall, Power, Mason, Stribley, Mathewson
"Statistical Worst-Case Analysis Techniques for CMOS Technology Using Design of Experiments"

K.Burke et al
"Worst-Case MOSFET Parameter Extraction for a 2um CMOS Process"
Proc. IEEE 1994 ICMTS, Vol. 7 pp. 119-125.

Power, Donnellan, Burke, Moloney, Mathewson, Lane
"Generation of MOS Model Parameters Covering Statistical Process Variations"
ESSDERC, 1993.

Power, Mathewson, Lane
"An Approach for Relating Model Parameter Variabilities to Process Fluctuations"

Power, Barry, Mathewson, Lane
"Accurate and Efficient Predictions of Statistical Circuit Performance Spreads"
IEEE CICC, 1992.

Power, Lane
"An Enhanced SPICE MOSFET Model Suitable for Analog Applications"
IEEE Trans CAD, 1992.

Power, Clancy, Wall, Mathewson, Lane
"An Investigation of MOSFET Statistical and Temperature Effects"

Power, Mathewson, Lane
"MOSFET Statistical Parameter Extraction Using Multivariate Statistics"

Power, Barry, Mathewson, Lane
"Worst-Case Simulation Using Principal Component Analysis Techniques: An Investigation"
ESSDERC, 1991.

Lin, Kuh, Marek-Sadowska
"Stepwise Equivalent Conductance Circuit Simulation Technique"
UC Berkeley, CA.

Lin, Mark-Sadowska, Kuh
"SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI"
UC Berkeley, CA.

Power, Lane
"Enhanced SPICE MOSFET Model for Analog Applications"

Moon Hyo Kang, Ji Ho Hur, Youn Duck Nam, Eun Ho Lee, Se Hwan Kim and Jin Jang
"An optical feedback compensation circuit with a-Si:H thin-film transistors for active matrix organic light emitting diodes", Journal of Non-Crystalline Solids, In Press, Corrected Proof, Available online 5 February 2008.

Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue,
"A Gate-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2,"
IEEJ Transactions on Electrical and Electronic
Engineering Vol. 3, Issue 1, Jan. 2008, pp. 64-71.

Y. Iino, I. Pesic,
"HiSIM- Replacement of BSIM4 in UDSM circuit simulations,"
2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, Vol. 3, 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, 2007, pp. 682-683.

Y. S. Yu
"A multi-gate single-electron transistor model for circuit simulations by SPICE", Journal of the Korean Physical Society, Vol. 50, No. 3, March 2007, pp. 739-743.

Y. S. Yu, S. W. Hwang, D. Ahn
"Transient modelling of single-electron transistors for efficient circuit simulation by SPICE"
IEE Proceedings: Circuits, Devices and Systems, Vol. 152, Issue 6, December 2005, pp. 691-696.

S. Mahapatra, A. M. Ionescu
"Realization of multiple valued logic and memory by hybrid SETMOS architecture"
IEEE Transactions on Nanotechnology, Vol. 4, Issue 6, November 2005, pp. 705-714.

X. Guo, S. R. P. Silva
"Investigation on the current nonuniformity in current-mode TFT active-matrix display pixel circuitry"
IEEE Transactions on Electron Devices, Vol. 52, Issue 11, November 2005, pp. 2379-2385.

K. Degawa, T. Aoki, H. Inokawa, T. Higuchi, Y. Takahashi
"A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors"
Proceedings of The International Symposium on Multiple-Valued Logic pp. 32-38.

C. Alaoui and Z. M. Salameh
"A novel thermal management for electric and hybrid vehicles"
IEEE Transactions on Vehicular Technology, Vol. 54, Issue 2, March 2005, pp. 468-476.

Katsuhiko Nishiguchi, Hiroshi Inokawa, Yukinori Ono, Akira Fujiwara, and Yasuwo Takahashi
"Multifunction Boolean Logic Using Single-Electron Transistors."
IEICE Trans. Electron. Vol E87 -C , No.11 November 2004

S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee, A. M. Ionescu
"Analytical modelling of single electron transistor for hybrid CMOS-SET analog IC design"
IEEE Transactions on Electron Devices, Vol. 51, Issue 11, November 2004, pp. 1772-1782.

H. Inokawa, Y. Takahashi, K. Degawa, T. Aoki, T. Higuchi
"A simulation methodology for single-electron multiple-valued logics and its application to a latched parallel counter"
IEICE Transactions on Electronics, Vol. E87-C, Issue 11, November 2004, pp. 1818-1826.

K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, Y. Takahashi
"A single-electron-transistor logic gate family for binary, multiple-valued and mixed-mode logic"
IEICE Transactions on Electronics, Vol. E87-C, Issue 11, November 2004, pp. 1827-1836.

X. Guo and S. R. P. Silva
"Circuit simulation of current-modulated field emission display pixel driver based on carbon nanotubes"
Electronics Letters, Vol. 40, Issue 18, September 2004, pp. 1113-1115.

A. M. Ionescu, S. Mahapatra, V. Pott
"Hybrid SETMOS architecture with Coulomb Blockade oscillations and high current drive"
IEEE Electron Device Letters, Vol. 25, Issue 6, June 2004, pp. 411-413.

A. Rahman and V. Polavarapuv
"Evaluation of low-leakage design techniques for field programmable gate arrays"
CM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Vol. 12, 2004, pp. 23-30.

H. Inokawa, Y. Takahashi, K. Degawa, T. Aoki, T. Higuchi
"A single-electron-transistor logic gate family and its application - Part II: Design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions"
Proceedings of The International Symposium on Multiple-Valued Logic 2004, pp. 269-274.

S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq, K. Banerjee, A. M. Ionescu
"SETMOS: A Novel True Hybrid SET- CMOS High Current Coulomb Blockade Oscillation Cell for Future Nano-Scale Analog Ics"
Technical Digest - International Electron Devices Meeting, 2003, pp. 703-706.

S. Mahapatra, K. Banerjee, F. Pegeon, A. M. Ionescu
"A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits"
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 2003, pp. 497-502.

H. Inokawa and Y. Takahashi
"Experimental and simulation studies of single-electron-transistor-based multiple-valued logic"
Proceedings of The International Symposium on Multiple-Valued Logic, 2003, pp. 259-266.

A. L. Sternberg, L. W. Massengill, S. Buchner, R. L. Pease, Y. Boulghassoul, M. W. Savage, D. McMorrow, R. A. Weller
"The role of parasitic elements in the single-event transient response of linear circuits"
IEEE Transactions on Nuclear Science, Vol. 49 I, Issue 6, December 2002, pp. 3115-3120.

A. L. Sternberg, L. W. Massengill, R. D. Schrimpf, P. Calvel
"Application determinance of single-event transient characteristics in the LM111 comparator"
IEEE Transactions on Nuclear Science, Vol. 48, Issue 6 I, December 2001, pp. 1855-1858.

J. -J. Wang, R. B. Katz, F. Dhaoui, J. L. McCollum, W. Wong, B. E. Cronquist, R. T. Lambertson, E. Hamdy, I. Kleyner, W. Parker
"Clock buffer circuit soft errors in antifuse-based field programmable gate arrays"
IEEE Transactions on Nuclear Science, Vol. 47, Issue 6 III, December 2000, pp. 2675-2681.

K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. -I Takagi, A. Toriumi
"Analytical single-electron transistor (SET) model for design and analysis of realistic SET circuits"
Japanese Journal of Applied Physics, Part 2: Letters, Vol. 39, Issue 4 B, 2000, pp. 2321-2324.

Pruvost, B., Mizuta, H., Oda, S
"3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs"
Nanotechnology, IEEE Transactions on Vol. 6, Issue 2, March 2007 pp. 218 - 224