SURGE Virtual Event China 2022

December 16, 2022 – 13:25 – 17:35 (China Standard Time)

Silvaco is pleased to invite you to join its annual Silvaco UseRs Global Event (SURGE), taking place virtually on December  16, 2022.

SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, share users’ experiences, and discover innovative techniques for advanced semiconductor design.

All attendees entered into the Lucky Draw win one of the following prizes:

  • DJI Mini SE Camera Drone
  • HUAWEI Watch GT 3
  • AirPods (3rd Gen) – with MagSafe Charging Case

(Please note all the appearance of prizes are subject to change) 

China Lucky Draw


1:00 PM
1:05 PM​
1:25 PM​Guest Speaker to be announced
1:45 PM​Challenges of Designing Quantum Computer SoCs – Jack Berg – VP of Operations – PsiQuantum
2:05 PMLucky Draw
2:15 PMBreak

2:30 PM
2:35 PM
3:05 PM
3:25 PM​
3:50 PM
4:00 PM
4:30 PM
4:50 PM
5:10 PM
5:25 PM
5:45 PMLucky Draw

2:30 PM
2:35 PMTo be announced - Xiaojun Guo - Shanghai Jiaotong University
3:00 PM​
3:30 PM​
4:00 PM​
4:20 PM​
4:40 PM
5:00 PMLucky Draw


SURGE 2022


Welcome and Introductions


赵友来 Ellison Zhao



Dr. Babak Taheri, Chief Executive Officer and Board Member
Silvaco, Inc.

Babak Taheri is the CEO and Member of the Board of Directors at Silvaco Group, a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. He also has been the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.

While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).

Babak was the recipient of “The Perfect Project Award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college. Dr. Taheri served as a member of the governing council on ESDA Alliance from 2019 to 2021 and served on the board of Parisi House on The Hill from June 2021 to May 2022.

He has held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. Babak received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences. He has over 20 published articles and holds over 30 issued patents. His most recent published book in 2021 is titled “Artificial Sensors Shape the Six Pillars of Our Lives”.

Challenges of Designing Quantum Computer SoCs



Speaker Bio:

Jack Berg – VP of Operations

Eric Guichard

TCAD Simulation Update


Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.


Dr Eric Guichard, Senior VP and GM of TCAD Division
Silvaco, Inc.

Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.

Dr. Guichard holds an MS in material science and a Ph.D in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.

Hemant Dixit

Revised Mobility Model for Predictive TCAD Simulations of 4H-SiC


Development of energy efficient next generations of Silicon Carbide (SiC) power MOSFETs is necessary to meet a growing demand for SiC technology from a wide range of applications that includes electric vehicles, solar inverters, power supplies, industrial motor drives and energy storage etc. Success of R&D efforts critically depends on ability to perform predictive TCAD simulations of SiC power MOSFETs. Although significant progress has been made in TCAD modelling of 4H-SiC, we observe that the existing set of models needs further improvements and calibration.

In this presentation, we focus on the bulk mobility model for 4H-SiC. We observe that the temperature dependence of bulk resistivity cannot be predicted accurately using the popular mobility models. A careful investigation reveals that these mobility models need to be revised and replaced by a comprehensive model that can describe the impurity scattering effects dominant at low temperatures. We present a well calibrated bulk mobility model for 4H-SiC exhibiting excellent agreement with measured data, making it suitable for device simulation purposes using TCAD tools.


Hemant Dixit, Ph.D.
Research Scientist, Wolfspeed, Inc.​​

Hemant holds PhD in Physics from University of Antwerp, Belgium and has been working in the Semiconductor industry for 10+ years. Prior to joining Wolfspeed, he worked at MOTOROLA, IBM and GLOBALFOUNDRIES. His expertise includes multiscale (both atomistic and continuum) modelling of semiconductor devices using TCAD tools. Hemant has published over 35 research articles with 1700+ citations and filed 15 patent applications (6 approved) with USPTO. At Wolfspeed, his focus is on improving the fundamental understanding of power MOSFETs, to accelerate the design and development efforts for next generation of devices.

Victory Atomistic – Updates on 2D Materials, CNTs, and How We Bridge Atomistic Simulations and TCAD


Performance predictions of nanodevices ideally include 1) atomistic resolution, 2) a consistent description of all quantum phenomena, and 3) a realistic treatment of incoherent scattering on phonons and impurities. It is common believe that atomistic quantum transport either entails unfeasible numerical load or neglects scattering effects altogether. Victory Atomistics indeed covers all 3 aspects, and this presentation showcases new modeling features in the realm of 2D materials and carbon nanotubes.

While Victory Atomistic covers all those points for only a small fraction of the typical numerical costs, some of the atomistic simulations might still take a few CPU hours to finish. Therefore, Silvaco’s and Purdue’s teams are bridging the gap between atomistic simulations and TCAD to enable reliable simulation results in TCAD typical simulation times.


Tillmann Kubis
Katherine Ngai Pesic and Silvaco Research Assistant Professor of Electrical and Computer Engineering
Purdue University

Prof. Dr. Tillmann Kubis is leader of Purdue’s NEMO5 development team. His research interest includes all topics of equilibrium and non-equilibrium phenomena in nanodevices and molecules. This covers electronic and phonon bandstructures as well as heat, charge, and spin transport in nanodevices. Dr. Kubis holds a Dr. rer. nat. in theoretical semiconductor physics from the Technische Universität München, Garching, Germany.

TCAD Modeling of the GaN-power Device Under Epi-structures Characteristics


The traps characterization based on the lateral and vertical device of growth GaN material on other substrates and results in high density of threading dislocation (the order of >108 cm-2). In order to improve the threading dislocation, previously; patterned-sapphire substrates (PSS) or nano patterned-sapphire substrates (NPSS) that can elevate the device optical/electrical characteristics, replace the plane-sapphire and the expensive SiC/free-standing GaN substrates. Using the TCAD simulation, resulting the traps affect the device performances within leakage current, hard-breakdown voltage, switch turn on/off, and especially the reliability issues. In addition, commercially, the productions of GaN-on-Silicon (Si) power device focuses on horizontal structures high electron mobility transistor (HEMT) with current collapse phenomenon to modify Epi-structures by TCAD.


Peter Chiu, Director of GaN power Electronic Device Department
HC Semitek

Dr. Chiu received the Ph.D. degree in engineering from Taiwan Ocean university, Taiwan, in 2009. (continued research in 3th semiconductor for epitaxy, processing, and TCAD simulation of GaN-power devices with lateral and vertical structures).
With more than 15 years of experience with GaN semiconductor manufacturing industry and design house, the publication and conference papers are more than 50s. He is currently the director with department of GaN power electronic device, HC (Zhejiang) Semitek Co., Ltd.

Analog Custom Design Update


Thomas Blasei will provide an update on Silvaco’s Analog Custom Design product portfolio, new features and functionality, and the future of Silvaco’s EDA solutions.


Thomas Blaesi, VP and GM of EDA Division
Silvaco, Inc​​​

Thomas F. Blaesi is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog customer design, circuit simulation and SPICE modeling. Thomas joined Silvaco in October 2017 and held the position of Vice President of Global Marketing until December 2019. He has more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Chung-Chun Chen

A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools


Chung-Chun Chen will go through an overview of Silicon Creations and our role as an IP vendor, which may include our achievements and products. The front-end challenges and solutions will be discussed, including our use of Gateway in addressing porting challenges between 12 different foundries in 180nm down to 3nm nodes. Then the back-end challenges and solutions will be also addressed, including our use of Expert. The final simulation challenges and solutions include our use of SmartSpice, Silos, and Variation Manager. This talk shows using Silvaco tools helps Silicon Creations’ IP development be efficient and robust from 3nm to 350nm.


​​​Chung-Chun Chen, Director of Analog Design
Silicon Creations 

Chung-Chun (CC) Chen has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia since being back in 2019. During 2018 – 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver/architect of Realtek’s high-speed Serdes technologies. During 2011 – 2018, CC was a senior analog designer/manager at Silicon Creations in Atlanta, Georgia while he designed analog IP products including Ring-based & LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia. Prior to this, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.

Chung-Chun (CC) Chen (S’02–M’09–SM’17) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.

VarMan Delivers Unprecedented High-Sigma Performance within a User-Friendly GUI Environment


Accuracy and flexibility have always been the core of VarMan technology. Today with the latest GUI redesign and algorithm enhancements, VarMan is entering a new era providing major improvements to the user experience that benefits from a wide customers’ feedback gathered along  years of worldwide deployment.

This new baseline version will be able to keep addressing new challenges and make variation analysis accessible to a larger audience.


Vincent Annezo, VarMan Corporate Application Engineer
Silvaco, Inc​​​.

Vincent is a Corporate Application Engineer dedicated to VarMan improvement and support. Prior to Silvaco, he worked as a Software Validation and Application Engineer at Aselta (French EDA start up) for 9 years. He earned a Master of Engineering degree in physics in 2003 from the engineering school INSA in Rennes, France.

Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso


In this presentation we will present the new features developed in Jivaro (parasitic reduction) and Viso (parasitic analysis and exploration) to tackle various challenges related to post layout interconnect parasitics. Latest Jivaro with its new “Pro” module is taking the parasitic reduction to a new era and enables unprecedented speed of SPICE simulations, especially for advanced process nodes. Viso has been enriched with new features to enable fast understanding and debug of parasitic structures without the need for long simulations.


Simon-Alexis Abric, Corporate Application Engineer
Silvaco, Inc.

Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Prior to Silvaco, he was an Application Engineer at Edxact SA for four years.

Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.

Design IP Solutions Update


Ben Louie will provide an update on Silvaco’s portfolio of Design IP, and its direction for the future.


Ben Louie, Associate Vice President of Foundation IP​
Silvaco, Inc​​​.

Ben Louie has over 22 years of experience in Memory Design including NOR Flash, NAND Flash, and MRAM. Most recently he was Director of Memory Design and Fellow at Spin Memory where he led their MRAM memory design efforts and was one of the primary inventors for their MRAM Engine IP. Prior to Spin Memory, Ben was Director of Design and Chief Design Engineer at Zeno Semiconductor where he worked on the development of a novel 1T SRAM memory. Additional startup experience also includes Magsil, a Field MRAM IP company. Before working startups, Ben worked at a few large semiconductor companies including Micron Technology and Xilinx. At Micron Technology, Ben led the Design team in the transition from NOR flash to NAND flash and was the design lead/manager for their first NAND products. Ben holds a Bachelor of Science Degree in Electrical Engineering and a Master of Science Degree in Electrical Engineering from Santa Clara University. He has been issued over 116 US Patents.

Dan FitzPatrick,

Cello FinFET Standard Cell Synthesis


Standard cells are form the lowest level foundation in the hierarchy of modern chip design architectures. FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to traditional planar layouts. However, the transition to FinFET technologies has come at the cost of increased standard cell design rule complexity. Many design rules violations can no longer be fixed within a local scope, since they may span a large region of a cell and interact with many layers, negatively impacting productivity for both initial design, migration and opportunities for specialization of standard cell libraries. In this talk we are going to review some of the most challenging aspects of FinFET standard-cell layout design, and how Silvaco Cello FinFET can be used to meet these challenges.


Dan Fitzpatrick, Associate VP of IP Software Development
Silvaco, Inc​​​

Dan Fitzpatrick is the Associate VP of IP Software Development for the Design IP group at Silvaco, in Santa Clara, California, where he leads the development of tools for IP design, characterization and management. He holds a Master of Science in Engineering from the University of Florida in Gainesville, Florida.

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TCAD as a Key Enabler for Photodiode Design


Photodiodes are a key technology to many growing application areas. Automotive vision systems, Advanced industrial machinery, and high-speed communications systems all rely on photodiodes to link optical inputs into usable electrical signal.

In this talk Silvaco will discuss these technologies, and how TCAD can be broadly applied to multiple detector topologies/material sets and thus multiple end-user markets. Additionally, we’ll detail simulation and analysis of an InGaAs Avalanche Photodiode. Through this demonstration, it will be shown how TCAD can be used to explore and characterize diode performance and extracting key Figures of Merit. Through TCAD, photodiode designers and technologists can increase their device performance, while decreasing engineering manufacturing and test cycles.


Sungwon Kong, Sr. Staff Field Applications Engineer
Silvaco, Inc

Sungwon Kong  has been supporting TCAD applications for digital displays beginning at Silvaco Korea in 1996. He graduated from Inha University in electrical materials and device engineering and worked at Samsung Electronics at Gi-heung, Kung-gi-do before joining Silvaco.

Jody Matos

Advanced TFT-Based Flat Panel Design with SmartSpice


This talk covers two extremely important aspects related to the design and simulation of Flat Panel Displays: 4-terminal TFT devices, and image retention.

Many TFT technologies in the market today are based on 4-terminal devices. In contrast, the SPICE simulators from other vendors can only support 3-terminal TFT compact models. Silvaco’s 4-terminal TFT model is unique in the market, and we will present some of the characteristics of this compact model, and some of the degrees of freedom that it brings to both modeling and the design teams.

Additionally, image retention is a long-standing issue in the display community. To effectively solve this issue, or even to minimize its impact on their products, display manufacturers and consumer electronics vendors need to simulate this effect at the SPICE level. We describe how SmartSpice Flex Modeling technology can be used to simulate image retention issues. This solution, which is unique to Silvaco, can model any dynamic device effects in SPICE simulation.


Jody Matos, Director of Circuit Simulation
Silvaco, Inc.

Dr. Jody Matos is a Ph.D. Computer Scientist who is passionate about research and development of software and hardware designs. Currently, he is the Director of Circuit Simulation at Silvaco, where he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to circuit simulation and analyses on analog, digital, and mixed-signal IC designs.

Dr. Matos received a Ph.D. degree in computer science from the Federal University of Rio Grande do Sul (UFRGS), Brazil, and a M.S. degree in microelectronics from the same institution. He has co-authored 30+ research papers and patent applications that mix knowledge of both computer science and microelectronics. Dr. Matos has also served as an expert reviewer and on technical committees of several renowned journals and international conferences in the fields of design automation.


Design and Simulate Emerging Devices for Display Technology


The flat panel display industry has been growing rapidly for recent years in mobile display, car display, AR/VR applications, and large-scale TVs display. The core technology enabling these applications is the light emitting diode (LED) technology, which is a key component to realize the highly visible, power efficient, displays. In this talk, we will discuss how to design and simulate the emerging devices such as Micro LED, QLED, OLED with Silvaco tools.


常志强 Kevin Chang, TCAD 技术支持部经理

长期从事 Silvaco TCAD 在国内的技术推广、客户支持等工作,致力于 TCAD 在半导体工艺和器件中的仿真应用,帮助客户建立 TCAD 仿真能力和平台。本科毕业于南京大学,硕士毕业于复旦大学。

4 Terminal TFT and OLED Compact Modeling


In this session Silvaco will present some of the 2022 Baseline enhancements to our Utmost IV Device Modeling tool. We will introduce the Corner and Retargeting Module, the most recent addition to our modeling software platform, and review some of the newest models and technologies where Silvaco’s Utmost IV is a key contributor. The presentation will conclude with a review of Silvaco’s modeling services through which our customers can benefit from our extensive SPICE modeling expertise.


Bogdan Tudor, Senior Manager, Device Characterization
Silvaco, Inc.​

Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.


Back-End-of-Line Compatible Amorphous Oxide Semiconductor Thin Film Transistor and Numerical Analysis of Oxygen Defects for Monolithic Three-dimensional Integrated Circuit Applications


The back-end-of-line (BEOL) compatible amorphous oxide semiconductor (AOS) thin-film transistor (TFT) is a suitable technology platform for the development of monolithic three-dimensional integrated circuits (M3D-ICs). In this work, n-channel amorphous indium tungsten oxide (a-IWO) nanosheet transistors have been successfully demonstrated in the class of InOx-based TFTs, especially with channel thickness scaling down to 4 nm. The integration of a-IWO nanosheet TFT with HfO2 gate insulator exhibits low operation voltages, good electrical characteristics: near ideal subthreshold swing ~ 63mV/dec., high field-effect mobility ~ 25.3 cm2/V-s. Through TCAD analysis, the effects of oxygen flow during a-IWO thin-film deposition on oxygen interstitials (Oi) defect at the front channel were numerically proved, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT.


Po-Tsun Liu – Chair Professor, Department of Photonics, National Yang Ming Chiao Tung University​

Prof. Po-Tsun Liu is currently a Chair Professor and Director of Display Research Center at National Yang Ming Chiao Tung University (NYCU) in Taiwan. He is a well-known specialist in TFT and TFT-based functional devices/circuits for TFT-LCDs and AMOLEDs, including amorphous oxide semiconductor (AOS)-based photo-sensors, nonvolatile memory devices (Flash, EEPROM, RRAM) and gate driver on array technologies. Furthermore, he extends the TFT technologies from flat-panel displays to the monolithic 3D-ICs application of advanced semiconductor engineering. He has published over 350 papers in peer-reviewed journals and international conferences, 1 Book and 1 Book chapter editor. He has given more than 100 invited presentations at international and national conferences. Additionally, Prof. Liu was elected IEEE Fellow (2020), SID Fellow (2021) and won the Outstanding Research Award (2021) from National Science and Technology Council (NSTC), in recognition of his unusual distinction in the profession and significant contributions to TFT technologies. He was named on the list of the World’s Top Electronics and Electrical Engineering Scientists (by He has also received numerous international conference paper awards, among other national awards in Taiwan, such as the Outstanding Engineering Professor Award from The Chinese Institute of Engineers (2022), Outstanding Electrical Engineering Professor Award from The Chinese Institute of Electrical Engineering in 2015, Excellent Young Scholar Research Grant, The Award for University Special Talents (National Science Council, from 2006-Present).

Prof. Liu’s lectures are always well-received by college students and researchers in FPD industries. For instance, he has won the Outstanding Teaching Award (NCTU, 2019) and has been praised four times by AUO at the annual Teacher’s Day celebrations (2015, 2016, 2018, 2020). Prof. Liu has been always dedicated to contributing himself to the work of scientific research and talent cultivation for many years.