• Sipex

Sipex Substrate Noise Extraction and Modeling

The development of RF front-end modules (FEM) — low-noise amplifiers (LNAs), power amplifiers (PAs), and RF switches —  for mmW and 5G applications can result in many silicon iterations, due to poor correlation between simulation and silicon measurements caused by substrate noise effects.  Sipex allows RF IC designers to model these effects accurately and easily with minimal impact on simulation times.

Sipex users see improved linearity in their RF designs while minimizing insertion loss and maximizing power efficiency and battery life. Because Sipex accurately models substrate noise, designers are free to explore novel layout structure that previously were too unpredictable in their effects.

Silvaco partners with leading edge silicon foundries with RF PDKs to offer a seamless solution that adds silicon substrate parasitic extraction with silicon-proven accuracy.  This means Sipex substrate noise analysis can be adopted by RF IC designers and applied to real designs in just one or two days.

Benefits seen by current users include:

  • Full-chip simulation of a SP9T switch, with hundreds of transistors and hundreds of MB of parasitics, completing in 30 minutes
  • Second and third harmonic simulation results within 3dB of silicon measurement
  • 25% reduction of total chip area due to accurate modeling of new and novel layout structures
  • >15 dB gain on second harmonic distortion

DP6T RF Switch Example

Sipex enables optimization of individual transistors and full-chip behavior. In the DP6T example shown above, the layout and geometry of the Thru or Shunt transistors are adjusted for the desired Ron, Coff, and linearity. Analysis of the coupling effects from the interconnects and devices to the silicon substrate for the entire switch is then done to verify the required full-chip behavior. Because of Sipex’s advanced modeling methods this happens quickly and easily. Sipex simulates noise effects previously seen only in silicon, as shown in the figure below.

Full-chip simulation of a SP6T switch showing silicon accurate results.

Analog Custom Design Resources

Analog Simulation
Analog Custom Design & Analysis
Model Generation
Guardian DRC
Utmost IVGuardian LVS
Parasitic Extraction
Gateway – Schematic CaptureJivaro– Parasitic Reduction for Fast, Accurate Simulation
Expert – Layout EditorViso – Parasitic Analyzer and Debugger
Guardian – DRC/LVS/Net Physical VerificationBelledonne – Layout Parastic Extraction Comparison
SmartSpice – Circuit SimulatorVarMan – Statistical Variation and Yield Analyzer
SmartView – Waveform AnalyzerVarMan XMA Option – Full-chip RAM Yield Analyzer
SmartSpice RadHard – Radiation Effects Circuit SimulatorVarMan for Libraries – Library Statistical Functional Verification
SmartSpice Pro– FastSPICE SimulatorUtmost IV– Device Characterization and SPICE Modeling
Hipex – Full-Chip Parasitic ExtractionUtmost IV Quick-Start– Model extraction and Optimization Templates
InVar IR – Drop and Thermal AnalysisTechModeler – Verilog-A Blackbox Device Modeling

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Customer Interview: Why I Rely on SmartSpice


Kunihisa Ishii
 More customers will be able to use our six-inch silicon foundry with our new 0.35 µm CMOS PDK for Silvaco custom design tools. With our partnership with Silvaco, who have a lot of experience in analog custom design solutions, we will reduce total development costs for our customers and extend our flexible foundry services.