The real world is analog and as more and more of a system is integrated onto a single SoC, the requirement for high accuracy analog design in mainstream processes becomes increasingly acute. At the same time, digital interfaces have to be designed as analog blocks. Not just SERDES but other interfaces such as DDRx, PCIe, USB3 and so on. Power management is becoming an increasingly critical aspect of any electronics system, be it a high end server or a mobile device. The arrival of FinFET processes, with a single transistor length and quantized transistor widths makes analog design of all sorts even more challenging. It is almost impossible to design a modern SoC without high-speed I/ O interfaces so this design needs to be efficient since it is typically on the critical path to tapeout.

High performance analog design, including the design of high-performance I/Os, is largely a manual process requiring a top-quality layout editor, a very accurate extractor and circuit simulation that supports a wide variety of analyses.

Silvaco’s suite of tools provides all of this. Layout has a wide range of foundry PDK support. It also supports OpenAccess iPDKs for ease of moving designs between different environments. Once layout is created the 3D extraction technology can be used for a full 3D field solver to extract the most accurate parasitics, including inductance, for high-sensitivity analog blocks.

Custom Design Flow and Foundry Partners

Silvaco’s circuit simulator provides golden SPICE accuracy. In particular the models are validated for TSMC’s FinFET nodes. Simulation supports transient noise analysis and RF analysis. For handling extracted netlists, which can be very large, there is high capacity parallel SPICE capability along with accurate RC reduction algorithms.

At advanced nodes there is increasing need to verify the power integrity of a design. This entails concurrent EM/IR/Thermal analysis which is available as an extension to Silvaco’s SPICE capability.

InVar-SmartSpice Power Integrity Signoff


  • 3D Parasitic Extraction for High Sensitivity Analog Blocks
  • 3D Extraction for Inductors
SPICE Simulation
  • Parallel SPICE for high accuracy
  • FastSPICE for Large Extracted Post-layout Simulation
  • AMS Simulation
  • Transient Noise Analysis
  • RF Analysis (PSS, PNOISE)
  • Virtuoso Integration
  • TSMC Model Certification for FinFET Nodes
Variation-Aware Design
  • Fast Monte Carlo analysis to save simulation runs; Local mismatch analysis
  • Statistical corners for quick design iterations
  • High sigma design for medical, automotive applications
Custom Design
  • Wide Range of Foundry PDK Support
  • OpenAccess iPDK Support
  • Full Custom Layout
  • Integrated Extraction and DRC/LVS
  • Integration with third party tools
Extracted Netlist Analysis & Reduction
  • Parasitic Reduction
  • Design Analysis
  • Comparison of extracted netlist with parasitics
  • Block to Full-chip Level Analysis
  • Early layout IR/EM analysis
  • SPICE Accuracy
  • TSMC Certified