Design of advanced CMOS processes starts with TCAD. It is too slow and expensive to run real wafers until relatively late, and much better to use rapid prototyping in TCAD to decide on an integrated flow followed by detailed simulation to determine process recipe details.


Silvaco has full pathfinding analysis for modern process architectures such as FinFET and FD-SOI, along with other novel devices. In the memory area, there is support for ion-enhanced etch, an important technology for vertical NAND flash, and STT MRAM.

3D FinFET Path-finding Simulation 3D NAND Flash IECE Etch Simulation


Standard BSIM models can be extracted from the TCAD models to form the link between the design of the new process and the tool environments which will be used to create the designs for manufacturing. There is a full 3D field solver to extract accurate parasitic data for FinFET SRAMs and other novel structures.

3D Parasitic Extraction for FinFET SRAM



  • Rapid Prototyping and Detailed Physical Simulation Modes
  • FinFET/Novel Device Pathfinding Analysis
  • FD-SOI Device Pathfinding Analysis
  • Advanced Ion-enhanced Etch for 3D NAND Flash and STT MRAM
  • Stress history
  • Laser annealing
  • Epitaxy
  • Diffusion & implantation in compound semiconductor
  • Robust Stable 3D Oxidation
  • 3D Parasitic RCX for FinFET SRAMs
Model Extraction
Extracted Netlist Analysis & Reduction
  • Parasitic Reduction
  • Design Analysis
  • Comparison of extracted netlist with parasitics
  • Belledonne for PDK update analysis, LPE qualification and design enablement