Verilog-A Release in SmartSpice

Introduction

We give in this article an introduction to the Verilog-A SmartSpice interface. This new feature in SmartSpice allows the user to write their own physical models in the Verilog-A language. The first section of the paper gives a brief overview of the Verilog-A language. The second presents the ease of use of simulating transistor models as well as digital circuits with the new Verilog-A SmartSpice interface.