Simulating the Effects of Stress/Strain on a 50 nm Silicon FinFET

1. Introduction

In modern semiconductor devices, the effects of physical lattice strain are playing an increasingly important role. One reason for this is that as device dimensions have shrunk, strains due to lattice mismatch or differences in thermal expansion have become more prevalent. Another is that strain has become an important tool in modifying and enhancing the electrical properties of the semiconductor materials [1]. Large strain induced gains in both electron and hole mobilities have been reported [2][3]. In this article, we will show how SILVACO tools can be used to simulate the creation of a 3D FinFET using VICTORY CELL, calculate the internal strains using VICTORY STRESS, and analyze its electrical characteristics using VICTORY DEVICE.