At design nodes 90nm and below, parasitic effects play a crucial role and substantially impact the behaviour of circuit design. These advanced technology nodes need better accuracy.

Silvaco’s tools for extracted netlist analysis & reduction combine performance, speed and accuracy. We offer a comprehensive suite of analysis tools to speed up the overall post-layout verification flow for Analog, Digital, RF, Mixed-signal & Memory design.

Product Overivew


JivaroJivaro™ is a netlist reduction platform. It speeds up the simulation time, increases accuracy and also reduces memory footprint. It is integrated into all major design flows and several graphical user interfaces.



BelledonneBelledonne™ is mainly used for layout parasitic extraction (LPE) flow qualification by running comparison of different extracted netlists.



VisoViso™ is an analysis tool that can carry out analysis on the electrical grid of parasitics. This parasitics‐centric approach allows for analysis times that are very short. Viso enables quick analysis of interconnect parasitics in order to pinpoint problems.