Design Analysis and Exploration

Viso™ is a tool that can carry out analysis on the electrical grid of parasitics. This parasitics-centric approach allows for analysis times that are very short. Viso enables quick analysis of interconnect parasitics in order to pinpoint problems. It allows timing estimation and accurate comparison of different extracted netlist.


At 90nm and below, parasitics on the interconnects crucially impact circuit behaviour. Their analysis is getting extremely important, since they impact gain, delay, maximum clock rate, cross-coupling, level of ESD protection and other features, which can even result in a complete failure.

Parasitics-related problems can be summarized to the following:

  • Intra-net pin to pin resistance (same net)
  • Intra-net pin to pin delay (same net)
  • Inter-net coupling capacitances
  • Inter-net decoupling capacitances
  • Intra-net pin to pin S/Y/Z parameters
  • Main current paths between different pins
  • Voltage drop along current paths
  • Electrical fields along current path


  • Viso provides unparalleled netlist analysis capabilities for all types of parasitic netlist components:
    • R, RC, RCC
    • Interconnects, substrate, package
  • Calculates the following pin to pin information
    • Intra-net pin to pin resistance and delay
    • Inter-net summary of coupling and decoupling capacitances between nets
    • Intra-net and Inter-nets pin to pin S/Y/Z parameters
  • Detection of shorts and opens
  • Calculations can be performed selectively on certain nets or groups of nets
  • Compatible with backend flows from all major EDA vendors
  • Integrated into all major design flows


  • Reduces backend verification cycle time
  • Improves probability of first silicon success
  • Early detection of gross errors
  • Increases effectiveness of backend flow: Simulation is launched only when the circuit has successfully passed analysis of interconnects

Fig: 1 2D and 3D view of a power grid


  • Memory, Analog, Mixed-signal, RF, Timing

Technical Specifications

  • Input: Extracted netlist generated by any LPE tool
  • Supports the Touchstone output format for S/Y/Z parameters
  • Application programming interface
  • Seamlessly integrates into existing design verification flow after LPE tool (layout parasitic extraction)  Ex- Cadence QRC, Mentor Calibre XRC, Synopsys RCXT