Typical high aspect ratio FinFET logic cell

RC Extractor for Realistic 3D Structures


Clever™ is a physics based resistance and capacitance field solver for any arbitrary shaped 3D structure. The structure can be created by Clever’s internal process simulator or can be loaded from Silvaco’s 3D Victory Process simulator. For MOS based applications, Clever also includes a netlist extractor and automatically back annotates field solved resistance and capacitance parasitics to this extracted active net list. For display applications, Clever LCD, an internal voltage dependent permittivity liquid crystal director physics solver, allows voltage dependent capacitance and optical transmittance simulations together with bias dependent director orientation.


  • Full 3D arbitrary shaped Resistance and Capacitance Physics Based Field Solver
  • Locally Varying Field Dependent, Physics Based, Liquid Crystal Permittivity
  • Liquid Crystal, Spacial and Voltage Dependent Director Orientation Solver
  • Voltage dependent optical transmittance solver for pattern visualization
  • Integrated Active Net List Extractor
  • Automated Back Annotation of Extracted C and R onto Extracted Net List.
  • Internal 3D Structure Creation or Imported from Victory 3D TCAD products.
  • Layout driven GUI Interface Option
  • Supports electrically floating and dummy conductors
  • Multiple user selectable solvers available
  • User Selectable Boundary Conditions, Material Properties and Solution Tolerance
  • Distributed Capacitance contributions to different regions from a single conductor
  • Middle End of Line (MEOL) FinFET capacitance analysis


Clever delivers the best accuracy, productivity and versatility for the most complicated interconnect cells, including realistic etching and deposition processes. Its local Adaptive Mesh Refinement (AMR) feature allows the user to specify a desired accuracy. Clever will automatically refine the unstructured mesh where required, optimizing maximum accuracy, together with minimum simulation time.


FinFet Applications

  • Middle End Of Line (MEOL) automated distributed capacitance calculations
  • Internal geometric processing capability, or
  • Import 3D structures from Silvaco’s Victory Process simulator


Typical high aspect ratio FinFET logic cell Capacitance from a single electrode can be correctly
distributed to multiple connected regions



Planar Technology

  • Integrated net list extraction
  • Automated back annotation of field solved back end resistance and capacitance



SEM photograph of an actual metal interconnect Comparison with field solved structure
imported from 3D Victory Process simulator




  • Large high aspect ratio flat panel capacitance simulations
Cut out of a representative matrix of cells
for simulation from the GDS-II file
Showing potential distribution and adaptive
meshing during capacitance calculations


LCD Technology

  • Field dependent Director distribution calculations
  • Field dependent capacitance calculations (C-V plots)
  • Different meshing and solver options



Potential distribution between two “chevron”
electrodes on an LCD surface
A cut-line through the center of the figure on the left,
showing LCD director positions at 6 volts


A capacitance versus voltage (C-V) plot of the structure shown in figure above Showing one of the meshing options, a Delaunay based mesh in this case



Average transmittance of a LC cell as a function of pixel voltages. Insets:
Light transmission patterns viewed from the top of the LC cell at different pixel voltages.
Average transmittance of a LC cell as a function of wavelengths with various pixel voltages.


Touch Panel

  • Electrically floating conductors correctly accounted for
  • Input syntax can contain variables such as finger height



3D structure emulating the approach of a
person’s finger towards the touch screen
Capacitance between two electrodes versus a person’s
finger height above the touch screen


Layout Driven Option

  • Clever RC extraction can be GUI driven, launched directly from Silvaco’s Expert layout tool
  • 3D structures are constructed using the known thickness of each layer



GUI interface invoked when using the layout driven option 3D structures automatically generated using layout driven GUI


Rev 050317_30