IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions

Verilog Simulator

Silos is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs.

Key Features

  • IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions
  • Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor
  • Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more
  • Supports compliance testing for RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,” Appendix B
  • Silvaco's strong encryption is available to protect valuable customer and third party intellectual property.


  • IEEE 1364 Compliant Verilog with 2001 Extensions including the generate statement and wildcards
  • Multi-level HDL simulator at switch, gate, and behavioral levels
  • Comprehensive Project Manager saves preferences, settings, directories, and options in a file for efficient multi-project setup
  • Save All enables designers to view the complete simulation history
  • Save and Restore saves the complete state of the simulator to a file that can be used to restart simulation at the point of the save
  • IEEE 1364 Programming Language Interface (PLI) enables designers and FPGA vendors to create Verilog extensions as dynamically linked libraries
Any Verilog expression can be viewed as a waveform by dragging and dropping the expression into the Data Analyzer.
Data Analyzer uses the Trace Signal Window and the Source Code Window to trace the cause of an unknown value.


Ease of Use

  • Easy-to-use graphic user interface provides productive environment for novices and experts—Silos selected by seven popular Verilog textbooks and used in the majority of university VLSI design courses
  • Hierarchy Explorer offers a familiar view of a hierarchical design with “drag & drop” for rapid capture and display of any variables in the design
  • Silos Interactive Environment enables real-time access and analysis of all expressions, variables, modules, signals, vectors, and registers
  • Consistent interactive methods for signal selection, setting time-scale, bus radix, status window, timing marker, bookmark, and bus definition
  • Interactive Source Code Editor displays line numbers for stop, start, and breakpoints, Data Tips to view the values of variables and expressions, and code coverage information

Productivity – Interactive Simulation Environment

  • High Performance simulation engine achieves fast simulation results rivaling compiled Verilog for interactive debugging of designs up to several hundred thousand gates (with no compile times)
  • Interactive, interpreted Verilog environment provides a set of multi-tasking utilities to edit HDL source, set incremental breakpoints, stepping or timed simulation, real-time viewing, and error detection
  • Multi-window customizable Data Analyzer controls pan and zoom, timing markers, using interactive “drag & drop” capture, and display for signals and expressions for analog and digital waveforms
  • Trace Mode graphically traces all fan-in connections to any signal through all levels of circuit hierarchy instantly
  • Watches window displays or forces state values of specified signals and variables while single-stepping – all set up through “drag & drop” for designer convenience
Data Tips in the Source Window display value, scope, and time of the highlighted expression at the T1 marker in the Data Analyzer.
Analog waveforms can be displayed in either piecewise linear format or stepping format.


Lint Capability

  • Checks for more than 500 design rules
  • Checks race conditions and clock domain synchronization
  • Checks for synthesizability, and reports potential synthesis and simulation mismatches
  • Optimizes gate usage with detailed reports of inferred registers, latches, state-machines and other sequential elements that will be synthesized into synchronous hardware
  • Extracts Finite State Machines (FSM) and analyses for redundant or unreachable states
  • Offers design-for-testability checks for up-front identification of un-testable circuits
  • Comprehensive report filtering system delivers precise information to isolate and fix problem

Support for FAA Standard DO254 Testing

RTCA/DO-254, DESIGN ASSURANCE GUIDANCE FOR AIRBORNE ELECTRONIC HARDWARE is a standard recognized by the Federal Aviation Administration (FAA) as a means to ensure the safety of electronic airborne systems by verifying the design of complex electronic hardware in airborne systems.

The Silos code coverage reporting feature supports compliance testing for RTCA/DO- 254 “Design Assurance Guidance for Airborne Electronic Hardware,” for levels A and B as specified to meet “Elemental Analysis” in Appendix B.

Silos generates code coverage reports including “Line/Statement Coverage,” “Operator/Expression Coverage” and “Branch Coverage.” Reports can be exported as text files and can also be examined interactively using the Silos graphical user interface (GUI). Code Coverage data from multiple independent simulation runs can be merged into a single report.

The user can enable and disable coverage reporting for specific lines and blocks of behavioral source code. Spurious time 0 events are automatically eliminated from the coverage results.

Silos Inputs/Outputs

Rev 042513_23