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Fast, intuitive and hierarchical LVS debugging with cross-probing to layout and schematic views

Guardian LVS and its Competitors
Mentor Graphics Calibre nmLVS, Cadence Assura Physical Verification, Synopsys Hercules, Magma Quartz LVS

Guardian LVS is a hierarchical layout versus schematic physical verification tool integrated with Silvaco’s schematic capture and layout editor. It provides interactive and batch mode verification of analog, mixed signal and RF IC designs. Guardian LVS can be used in place of Calibre nmLVS, Assura, Hercules, Quartz LVS providing the following key features:

  • Guardian LVS is integrated with Expert Layout Editor, Gateway Schematic Editor, and Hipex for parasitic RC extraction
  • Efficient full-chip layout netlist extraction for any semiconductor process with unmatched performance
  • Accurate calculation of geometry-dependent SPICE parameters important for analog design with default or user-defined equations
  • Precise identification of generic devices (transistors, diodes, resistors, capacitors, etc.), user-defined devices, and/or black-box subcircuits during LVS trace
  • Supports stress effects and well proximity parameter extraction
  • Handles any arbitrary shaped polygon geometry used in device formation
  • Maximum preservation of original hierarchy for easy debugging during post-layout
  • Detects ERC violations (shorts, opens, dangles, and improperly connected devices) with convenient filtering options
  • Intuitive hierarchical LVS discrepancy report significantly decreases time for error debugging
  • Hierarchical cross-probing of schematic netlist, extracted layout netlist, physical layout, and schematic design
  • Multi-threading for hierarchical netlist comparison
  • PDKs are available for leading foundry processes from TSMC, UMC, Jazz/TOWER, X-Fab, Austriamicrosystems, MOSIS, AMI and others

Mentor Calibre, Cadence Assura, Synopsys Hercules, Magma Quartz are trademarks of their respective owners.