True SPICE accuracy for simulating full chip static, dynamic and leakage power for signal integrity of clock trees with extended parasitics and victim/aggressor nets

Parallel SPICE Circuit Simulator

Silvaco’s SmartSpice™ is a high performance parallel SPICE simulator that delivers industry leading accuracy. It is a proven, comprehensive solution for applications including simulation of complex high precision analog and mixed-signal circuits, memory, custom digital design and characterizing cell libraries of advanced semiconductor processes.


Circuit simulation has been fundamental to the development of electronic devices for many years. Now, shrinking silicon geometries are forcing an even greater premium on accuracy in order to capture and evaluate all the new physical effects in nanometer design. Yet they also often pose extreme requirements on simulation capacity and performance. Traditional SPICE tools may provide sufficient accuracy, but run too slow or suffer significant capacity constraints. FastSPICE-type products attempt to meet performance requirements but sacrifice accuracy. Both are increasingly unacceptable compromises. 

Silvaco’s SmartSpice uses an intelligent architecture deploying multiple solvers, stepping algorithms and computation techniques. The result is accurate, robust convergence and industry leading performance and capacity – over 8 million active devices. It is compatible with HSPICE and Spectre for netlists, models, analysis features, and results – plus large libraries of calibrated device models are available. Featuring integration with Silvaco Gateway schematic editor and SmartView waveform viewer, SmartSpice fits seamlessly into front-end analog IC design flows.


  • HSPICETM and SpectreTM compatible for netlists, models, analysis features and results
  • Large collection of calibrated SPICE models for traditional (Bipolar, CMOS) and advanced technologies (TFT, OTFT, SOI, HBT, FRAM, FinFET etc.)
  • Verilog-A based open model development environment and debug, with extensive analog behavioral capability
  • Unique Rubberbanding feature that allows designer to modify model, instance and user-defined parameters and interactively see in SmartView how the simulation changes in real time
  • Integrated with cell characterization products AccuCell XT and AccuCore XT
  • All models support advanced convergence algorithms, temperature dependencies, montecarlo simulation.
  • Batch and interactive modes of operation, plus ability to run directly from the Gateway Schematic Capture environment
  • Parallel simulation using multiple 64-bit CPUs for near linear speedup
  • Network distributed Monte- Carlo and worst case analysis
  • SEE (Single Event Effects) reliability analysis for nanometer scale designs
  • Silvaco SPICE modeling services are available to extract DC, AC, S-parameters, capacitance, temperature, noise and SPICE parameters over full temperature and corner model statistical analysis


  • Delivers the accuracy, capacity, and simulation performance required for critical complex analog and mixed-signal designs at nanometer silicon nodes
  • Easy integration into analog front-end flows with support of standard design formats, languages and tools


  • Analog, mixed-signal
  • Memory design
  • FPD design
  • Custom digital
  • Library Characterization

Technical Specifications

  • Supported industry standard netlist format: Berkeley SPICE, HSPICE and Spectre netlists, S-parameter files, W-element RLGC matrix files, S-parameter model files, Verilog-A
  • Output formats: rawfiles, Spectre PSF, HSPICE tr0 and mt0, analysis results, measurement data
  • Compatibility with HSIM, Spectre, Eldo
  • Rich analysis feature set including AC, DC, transient, noise, distortion, operating point, pole- zero, FFT and noise analysis
  • Supported DSPF back-annotation and RLC reduction on netlist