• Viso

Viso Parasitic Analyzer and Debugger

Viso analyzes the electrical properties of RC parasitic networks which crucially impact circuit behavior in nanometer processes. These impacts affect circuit gain, delay, maximum clock rate, cross-coupling, level of ESD protection and other features, which can cripple a design.  Viso’s parasitics-focused approach enables quick analysis of interconnect in order to pinpoint problems. It provides timing estimation and accurate comparison of different extracted netlists.

Features

Viso provides unparalleled netlist analysis capabilities for all types of parasitic netlist components:

  • R, RC, RCC
  • Interconnects, substrate, package

It can detect shorts and open nets and calculations can be performed selectively on certain nets or groups of nets

It calculates the following pin to pin information:

    • Intra-net pin to pin resistance and delay
    • Inter-net summary of coupling and decoupling capacitances between nets
    • Intra-net and Inter-nets pin to pin S/Y/Z parameters

Viso is integrated into all major circuit design flows

Benefits

  • Quickly answers designers’ questions about their post-layout parasitic netlist, such net-to-net and pin-to-pin characteristic matching
  • Reduces backend verification cycle time
  • Improves probability of first silicon success
  • Early detection of gross errors
  • Increases effectiveness of backend flow: Simulation is launched when the circuit has successfully passed interconnect analysis
  • Debug of post-layout tool flow

Applications

  • Memory, analog, mixed-signal, RF, timing

Parasitic Reduction & Analysis Resources

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Customer Interview: Why I Rely on SmartSpice

Customers

Cameron Fisher
 MSC has found SmartSpice™ to be an excellent value in terms of easy integration, debug run time and total cost of simulation. Support during our learning curve has been great. MSC will be using SmartSpice™ for all future memory complier development.