Silicon Creations Taps Silvaco’s Custom Design Flow For 10nm FinFET Designs
Flexible Layout Editor Speeds Successful Tape-out and Silicon Delivery
Santa Clara, California – May 25, 2016 – Silicon Creations, a supplier of high-performance semi-custom analog and mixed-signal intellectual property (IP), and Silvaco, Inc., a leading supplier of Electronic Design Automation (EDA) software, today announced that Silvaco’s Custom Design Flow has been successfully deployed for 10nm silicon node designs. Silicon Creations utilized a number of Silvaco’s products, including Gateway schematic editor, Expert hierarchical IC layout editor, and SmartSpice analog circuit simulator.
Over the 8-year partnership between the companies, Silicon Creations successfully created multiple products using their design flow and Silvaco products. When it came time to design at the 10nm process node, they rapidly extended this flow to get the tapeout done on time&even in the face of updates to the silicon design rules that arrived just a few weeks prior to tapeout. Silicon Creations’ IP market requires they be among the first to adopt new silicon process nodes, necessitating the use of very early versions of the process design kits (PDKs). These evolve rapidly and hence require a flexible but automated flow and layout tools to adapt the design to PDK updates.
“As an IP provider, the ability to efficiently port designs to the latest advanced processes, and adapt to changing process requirements is essential,” said Randy Caplan, principal and co-founder of Silicon Creations. “We took advantage of Silvaco’s custom capabilities, including Expert’s flexible scripting, that we optimized to quickly support our recent 10nm designs. We are continuing to push the next generation process technology with upcoming designs using Silvaco’s products.”
Silvaco Products used in Silicon Creations’ 10nm design flow included:
- Gateway&a hierarchical schematic editor tool that provides a complete environment to allow designers to visualize and capture their design in the form of schematics
- Expert&a high-performance, hierarchical IC layout editor with full editing features, large capacity and fast layout viewing
- SmartSpice – a high performance simulator that delivers accuracy for complex, high precision analog and mixed-signal circuits
“10nm FinFET design rules significantly increase complexity and can create schedule challenges for teams,” said Dave Dutton, CEO of Silvaco. “Therefore the on-time success of Silicon Creations’ 10nm projects shows the power of selecting advanced and flexible custom design tools, including Silvaco’s Expert layout editor that can be optimized for multiple process nodes and foundries. We look forward to continuing to support Silicon Creations in their IP development on current and future technology nodes.”
About Silicon Creations
Silicon Creations is focused on providing world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), SerDes and high-speed differential I/Os. Silicon Creations’ IP is in mass production from 16- to 180-nanometer process technologies. With a complete commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation.
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About Silvaco, Inc.
Silvaco, Inc. is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Silvaco delivers a full TCAD-to-signoff flow for vertical markets including: displays, power electronics, optical devices, radiation and soft error reliability and advanced CMOS process and IP development. For over 30 years, Silvaco has enabled its customers to bring superior products to market at reduced cost and in the shortest time. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.