![\"Banner](\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\")
<\/p>\n<\/p>\n
Abstract<\/strong><\/p>\n In this webinar, we show how Silvaco\u2019s Victory Atomistic \u2013 a quantum transport device \u00a0simulator \u2013 can be used to fulfil these requirements. Victory Atomistic is built on the Non-Equilibrium Green’s Function (NEGF) formalism with a full tight-binding band structure. Thanks to a proprietary Low Rank Approximation (LRA) technique and an optimized semi-unitary matrix database, Victory Atomistic achieves up to 10\u2075\u201310\u2076\u00d7 speed-up over conventional NEGF solvers, allowing the simulation of a full nanoelectronic device whilst delivering full-band accuracy at effective-mass speed. We demonstrate how Victory Atomistic, seamlessly integrated with Silvaco\u2019s leading AI-powered FTCO\u2122 workflow based on Victory DoE and Victory Analytics, forms a fast and integrated quantum transport solution which enables rapid prototyping as well as design exploration and optimization of GAA-NS-FETs \u2014 including key figures of merit such as DIBL, Vth<\/sub>, SS, and injection velocity \u2014 across a wide range of geometries, materials, and temperatures.<\/p>\n What You Will Learn<\/strong><\/p>\n Dr. Philippe Blaise is a Principle Engineer in Silvaco\u2019s TCAD Business Unit and leads the Victory Atomistic developments. Prior to joining Silvaco, Dr. Blaise was a Senior Engineer specialized in atomistic simulation of emerging memory devices and transistors at CEA\/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He published more than 60 journal articles and 30 conference contributions as well as 5 patents. Dr. Blaise holds a master\u2019s degree in applied mathematics from ENSIMAG, France and a Ph.D. in solid states physics from the Universit\u00e9 Grenoble Alpes, France.<\/p>\n Device simulation engineers, product managers, and engineering management.<\/p>\n![\"\"](\"https:\/\/silvaco.com\/wp-content\/uploads\/2026\/05\/VA_webinar_image.jpg\")
As CMOS technology scales toward the 2nm node and beyond into the \u00c5ngstr\u00f6m era, Gate-All-Around Nanosheet FETs (GAA-NS-FETs) have become the architecture of choice for next-generation logic devices. At these dimensions, quantum effects can no longer be neglected, and the electronic band structure becomes device-dependent.<\/p>\n\n
Presenter<\/h2>\n
![\"Philippe](\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/08\/Philippe-Blaise.jpg\")
Dr. Philippe Blaise<\/strong>
\nPrinciple Engineer, Silvaco<\/strong><\/p>\nWHO SHOULD ATTEND:<\/h3>\n
\nRegister!<\/h1>\n