{"id":31715,"date":"2020-02-26T02:07:34","date_gmt":"2020-02-26T02:07:34","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/cmos-technology\/"},"modified":"2020-02-26T02:07:34","modified_gmt":"2020-02-26T02:07:34","slug":"cmos-technology","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/tcad-ko\/tcad-published-papers-ko\/cmos-technology\/","title":{"rendered":"CMOS Technology"},"content":{"rendered":"
\n

CMOS Technology<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

T Uchino1, 2,<\/sup>\u00a0E Gili1, 3,<\/sup>\u00a0L Tan4,<\/sup>\u00a0O Buiu4,<\/sup>\u00a0S Hall4<\/sup>\u00a0and P Ashburn1<\/sup>,
\n“Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure”<\/p>\n

    \n
  1. School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, UK<\/li>\n
  2. Department of Electronics and Intelligent Systems, Tohoku Institute of Technology, Sendai, 982-8577, Japan<\/li>\n
  3. Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE, UK<\/li>\n
  4. Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool, L69 3GJ, UK<\/li>\n<\/ol>\n

    B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet,
    \n“In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation”,
    \nSolid-State Electronics, Vol. 57, Issue 1, March 2011, pp. 67\u201372.<\/p>\n

    Chi-Woo Lee, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, Jean-Pierre Colinge,
    \n“Performance estimation of junctionless multigate transistors”,
    \nSolid-State Electronics, Vol. 54, Issue 2, February 2010, pp. 97-103.<\/p>\n

    V. Vasireddy, S. Parke,
    \n“Simulation and Experimental Results of a 0.15\u00b5m Independent Double Gated CMOS Transistor”,
    \n2010 18th Biennial University\/Government\/Industry Micro\/Nano Symposium (UGIM), 2010, pp. 1 – 3.<\/p>\n

    F. Salehuddin, I. Ahmad, F.A Hamid, A. Zaharim,
    \n“Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method”,
    \n2010 IEEE International Conference on Semiconductor Electronics (ICSE), 2010, pp. 19 – 24.<\/p>\n

    A. Abdul Aziz, S. S. Osman,
    \n“A Simulation based study on C-V characteristics of oxide thickness for NMOS”,
    \n2010 Intl Conf on Electronic Devices, Systems and Applications (ICEDSA), 2010, pp. 404 – 407.<\/p>\n

    Sarvesh Dubey, Pramod Kumar Tiwari, S. Jit,
    \n“A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile”,
    \nJournal of Applied Physics, Vol. 108 , Issue: 3, 2010, pp. 034518 – 034518-7.<\/p>\n

    P. Rakesh Kumar, Santanu Mahapatra,
    \n“Analytical modeling of quantum threshold voltage for triple gate MOSFET”,
    \nSolid-State Electronics, Vol. 54, Issue 12, December 2010, pp. 1586-1591.<\/p>\n

    A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, G. Pananakakis, N. Collaert,
    \n“Analytical modelling for the current\u2013voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs”,
    \nMicroelectronic Engineering, Vol. 87, Issue 9, November 2010, pp. 1764-1768.<\/p>\n

    M. Cheralathan, A. Cerdeira, B. I\u00f1iguez,
    \n“Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations”,
    \nSolid-State Electronics, In Press, Corrected Proof, Available online 23 September 2010.<\/p>\n

    M. Najmzadeh, K. Boucart, W. Riess, A.M. Ionescu,
    \n“Asymmetrically strained all-silicon multi-gate n-Tunnel FETs”,
    \nSolid-State Electronics, Vol. 54, Issue 9, September 2010, pp. 935-941.<\/p>\n

    Munawar A. Riyadi, Ismail Saad, Razali Ismail,
    \n“Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET”,
    \nMicroelectronics Journal, In Press, Corrected Proof, Available online 22 July 2010.<\/p>\n

    U. Monga, H. B\u00f8rli, T. A. Fjeldly,
    \n“Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs”,
    \nMathematical and Computer Modelling, Vol. 51, Issues 7-8, April 2010, pp. 901-907.<\/p>\n

    K. Park, P. Nayak, D.K. Schroder,
    \n“Role of the substrate during pseudo-MOSFET drain current transients”,
    \nSolid-State Electronics, Vol. 54, Issue 3, March 2010, pp. 316-322.<\/p>\n

    Woo Young Choi,
    \n“Applications of impact-ionization metal\u2013oxide-semiconductor (I-MOS) devices to circuit design”,
    \nCurrent Applied Physics, Vol. 10, Issue 2, March 2010, pp. 444-451.<\/p>\n

    K. Romanjek, E. Augendre, W. Van Den Daele, B. Grandchamp, L. Sanchez, C. Le Royer, J.-M. Hartmann, B. Ghyselen, E. Guiot, K. Bourdelle, S. Cristoloveanu, F. Boulanger, L. Clavelier,
    \n“Improved GeOI substrates for pMOSFET off-state leakage control Microelectronic Engineering”,
    \nIn Press, Corrected Proof, Available online 16 March 2009.<\/p>\n

    Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R. S. Gupta,
    \n“cwith gate stack configuration”,
    \nMicroelectronic Engineering, In Press, Corrected Proof, Available online 17 January 2009.<\/p>\n

    P. Martin, M. Cavelier, R. Fascio, G. Ghibaudo, M. Bucher,
    \n“EKV3 compact modeling of MOS transistors from a 0.18\u00a0\u03bcm CMOS technology for mixed analog\u2013digital circuit design at low temperature Cryogenics”,
    \nIn Press, Corrected Proof, Available online 1 January 2009.<\/p>\n

    Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R.S. Gupta,
    \n“Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration”,
    \nMicroelectronic Engineering, Vol. 86, Issue 10, October 2009, pp. 2005-2014.<\/p>\n

    Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
    \n“TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”,
    \nSuperlattices and Microstructures, Vol. 46, Issue 4, October 2009, pp. 645-655.<\/p>\n

    Xi Liu, Xiaoshi Jin, Jong-Ho Lee,
    \n“A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs”,
    \nSolid-State Electronics, Vol. 53, Issue 9, September 2009, pp. 1041-1045.<\/p>\n

    Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R.S. Gupta,
    \n“Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration”,
    \nMicroelectronic Engineering, Vol. 86, Issue 10, October 2009, pp. 2005-2014.<\/p>\n

    Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta,
    \n“TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation”,
    \nSuperlattices and Microstructures, Vol. 46, Issue 4, October 2009, pp. 645-655.<\/p>\n

    Xi Liu, Xiaoshi Jin, Jong-Ho Lee,
    \n“A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs”,
    \nSolid-State Electronics, Vol. 53, Issue 9, September 2009, pp. 1041-1045.<\/p>\n

    B. Ayub, M. Rusop,
    \n“The effect of gate dielectric thickness on PMOS performance”,
    \nAIP Conference Proceedings, Vol. 1136, 2009, pp. 560-564.<\/p>\n

    O. Suziana, B. Ayub, M. Redzuan, A. R. Shahrir, M. Y. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
    \n“Effect of doping concentration on electrical characteristics of NMOS structure”,
    \nAIP Conference Proceedings, Vol. 1136, 2009, pp. 575-580.<\/p>\n

    M. Redzuan, B. Ayub, M. Shahrir, O. Suziana, M. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
    \n“Mesh grid of SILVACO TCAD effect on net doping profile for NMOS structures”,
    \nAIP Conference Proceedings, Vol. 1136, 2009, pp. 581-585.<\/p>\n

    A. R. Shahrir, M. Rusop,
    \n“The threshold voltage properties of NMOS structure etched with different etching methods”,
    \nAIP Conference Proceedings, Vol. 1136, 2009, pp. 555-559.<\/p>\n

    Woo Young Choi,
    \n“Applications of impact-ionization metal-oxide-semiconductor (I-MOS) devices to circuit design”,
    \nCurrent Applied Physics, In Press, Corrected Proof, Available online 3 July 2009.<\/p>\n

    Chang-Hoon Kim1<\/sup>, Cheulhee Jung2<\/sup>, Hyun Gyu Park2<\/sup>\u00a0& Yang-Kyu Choi1<\/sup>
    \n“    Novel Dielectric-Modulated Field-Effect Transistor for Label-Free DNA Detection<\/a>”<\/p>\n

      \n
    1. Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Republic of Korea<\/li>\n
    2. Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Republic of Korea
      \nBiochip Journal, Vol. 2, No. 2, 127-134, June 2008<\/li>\n<\/ol>\n

      Ratul Kumar Baruah, Santanu Mahapatra,
      \n“Justifying threshold voltage definition for undoped body transistors through \u201ccrossover point\u201d concept”,
      \nPhysica B: Condensed Matter, Vol. 404, Issues 8-11, 1 May 2009, pp. 1029-1032.<\/p>\n

      Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta,
      \n“Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI”,
      \nMicroelectronic Engineering, Vol. 85, Issue 3, March 2008, pp. 566-576.<\/p>\n

      Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta,
      \n“Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI”,
      \nMicroelectronic Engineering, Vol. 85, Issue 3, March 2008, pp. 566-576.<\/p>\n

      Lizhe Tan, Octavian Buiu, Stephen Hall, Enrico Gili, Takashi Uchino, Peter Ashburn,
      \n“The influence of junction depth on short channel effects in vertical sidewall MOSFETs”,
      \nSolid-State Electronics, Vol. 52, Issue 7, July 2008, pp. 1002-1007.<\/p>\n

      F. Lime, B. Iniguez, O. Moldovan,
      \n“A quasi-two-dimensional compact drain-current model for undoped symmetric double-gate MOSFETs including short-channel effects”,
      \nIEEE Transactions on Electron Devices, Vol. 55, No. 6, June 2008, pp. 1441-1448.<\/p>\n

      S. Capraro1<\/sup>, C. Bermond1<\/sup>, T.T. Vo1<\/sup>, J. Piquet1<\/sup>, B. Fl\u00e9chet1<\/sup>, M. Thomas2<\/sup>, A. Farcy2<\/sup>, J. Torres2<\/sup>, S. Cremer2, E. Guichard3<\/sup>, A. Haen3<\/sup>,
      \n”\u00a0“Design Improvement of RF 3D MIM Damascene Capacitor “”<\/p>\n

        \n
      1. LAHC, IMEP-LAHC, Universit\u00e9 de Savoie, Campus Scientifique, 73736 Le Bourget du Lac, France<\/li>\n
      2. STMicroelectronics, 850 rue J. Monnet, 38926 Crolles cedex, France<\/li>\n
      3. Silvaco Data Sytems, 55 rue Pascal Blaise, 38330 Montbonnot St Martin, France<\/li>\n<\/ol>\n

        Yu. P. Snitovsky, M. G. Krasikov,
        \n“New CMOS process using a thermal-oxide mask for making n–<\/sup>\u00a0– and p–<\/sup>\u00a0– wells”,
        \nRussian Microelectronics, Vol. 37, No. 3, May 2008, pp. 166-174.<\/p>\n

        A. S. Zoolfakar, H. Hashim,
        \n“Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor”,
        \nSecond Asia International Conference on Modeling & Simulation,
        \n2008. AICMS 08. 13-15 May 2008 pp. 1061 – 1064.<\/p>\n

        S. F. W. M. Hatta, N. Soin,
        \n“Design of a low voltage CMOS LNA at 2 GHz with substrate-bias”,
        \nAIP Conference Proceedings, Vol. 1060, 2008, pp. 244-249<\/p>\n

        Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
        \n“Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI”,
        \nMicroelectronic Engineering, Vol. 85, Issue 3, Mar. 2008, pp. 566-576.<\/p>\n

        Zoolfakar A. S., Hashim H.,
        \n“Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor”,
        \nSecond Asia International Conference on Modeling & Simulation, AICMS 2008. 13-15 May 2008, pp. 1061-1064.<\/p>\n

        Harsupreet Kaur, Sneha Kabra, Subhasis Haldar and R.S. Gupta,
        \n“An analytical drain current model for graded channel cylindrical\/surrounding gate MOSFET”,
        \nMicroelectronics Journal, Vol. 38, Issue 3, March 2007, pp. 352-359.<\/p>\n

        Kathy Boucart and Adrian Mihai Ionescu,
        \n“Double-Gate Tunnel FET With High- k Gate”
        \nIEEE Transactions on Electron Devices, VOL 54, NO 7, July 2007<\/p>\n

        F. Mayer, C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier and S. Deleonibus,
        \n“Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)”,
        \nSolid-State Electronics, Vol. 51, Issue 4, April 2007, pp. 579-584.<\/p>\n

        X. Loussier, D. Munteanu and J. L. Autran,
        \n“Impact of high-permittivity dielectrics on speed performances and power consumption in double-gate-based CMOS circuits”,
        \nJournal of Non-Crystalline Solids, Vol. 353, Issues 5-7, 1 April 2007, pp. 639-644.<\/p>\n

        Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park,
        \n“Design and simulation of asymmetric MOSFETs “,
        \nIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-C, No. 5, May 2007, p 978-982.<\/p>\n

        Ulrich Abelein, Andreas Assmuth, Peter Iskra, Markus Schindler, Torsten Sulima and Ignaz Eisele,
        \n“Doping profile dependence of the vertical impact ionization MOSFET\u00b4s (I-MOS) performance”,
        \nSolid-State Electronics, Vol. 51, Issue 10, October 2007, pp. 1405-1411.<\/p>\n

        Jong Pil Kim (Seoul Nat. Univ., Seoul, South Korea), Woo Young Choi, Jae Young Song, Sang Wan Kim, Jong Duk Lee; Byung-Gook Park,
        \n“Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure”,
        \nIEEE Transactions on Electron Devices, Vol. 54, No. 11, Nov. 2007, pp. 2969-2974.<\/p>\n

        P. K. Ooi, K. Ibrahim,
        \n“Simulation of single channel length vertical silicon MOSFET”,
        \nAIP Conference Proceedings, Vol. 1017, 2007, pp. 154-158.<\/p>\n

        S. Michael, L.T.B. Canfield,
        \n“The design and optimization of advanced thermophotovoltaic devices for deep space applications using a new modeling approach”,
        \nAIP Conference Proceedings, Vol. 890, No. 1, 2007, pp.s 213-226.<\/p>\n

        G. M. Buiatti, F. Cappelluti, G. Ghione,
        \n“Physics-based PiN diode SPICE model for power-circuit simulation”,
        \nIEEE Transactions on Industry Applications, Vol. 43, No. 4, July-August 2007, pp. 911-919.<\/p>\n

        I. V. Kotova, T. J. Humanica, D. Nouaisb, J. Randela, A. Rashevskyc,
        \n“Electric fields in nonhomogeneously doped silicon. Summary of simulations”
        \nNuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 568 (1), pp. 41-45, July 10 2006.<\/p>\n

        M. Elgin, D. Russell, M. Katula, R. Paulsen, S. Parke,
        \n“CMOS imager pixel design for space applications”,
        \nMicroelectronics and Electron Devices, 2006. WMED ’06. 2006 IEEE Workshop on 14 April 2006, pp. 1.<\/p>\n

        Vaskar Sarkara and Aloke K. Dutta,
        \n“An accurate, analytical, and technology-mapped definition of the surface potential at threshold and a new postulate for the threshold voltage of MOSFETs”
        \nSolid-State Electronics Vol. 50, Issues 11-12, November-December 2006, pp. 1814-1821.<\/p>\n

        M. Masahara, Y. Liu, K. Ishii, K. Sakamoto, T. Matsukawa, H. Tanoue, S. Kanemaru, E. Suzuki,
        \n“Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors”
        \nApplied Physics Letters, Vol. 86, Issue 12, 21 March 2005, pp. 1-3.<\/p>\n

        K. K. Bhuwalka, J. Schulze, I. Eisele,
        \n“Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering”
        \nIEEE Transactions on Electron Devices Vol. 52, Issue 5, May 2005, pp. 909-917.<\/p>\n

        K. Chong, X. Zhang, K.-N. Tu, D. Huang, M.-C. Chang, Y.-H. Xie,
        \n“Three-dimensional substrate impedance engineering based on p-\/p+ Si substrate for mixed-signal system-on-chip (SoC)”
        \nIEEE Transactions on Electron Devices, Vol. 52, Issue 11, November 2005, pp. 2440-2446.<\/p>\n

        P. Kasturi, M. Saxena, R. S. Gupta,
        \n“Modeling and simulation of STacked Gate Oxide (STGO) architecture in Silicon-On-Nothing (SON) MOSFET”
        \nSolid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1639-1648.<\/p>\n

        M. De Souza, M. A. Pavanello, B. Iniguez, D. Flandre,
        \n“A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation”
        \nSolid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1683-1692.<\/p>\n

        G. Nicholas, T. J. Grasby, E. H. C. Parker, T. E. Whall, T. Skotnicki,
        \n“Evidence of reduced self-heating in strained Si MOSFETs”
        \nIEEE Electron Device Letters, Vol. 26, Issue 9, September 2005, pp. 684-686.<\/p>\n

        M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, E. Suzuki,
        \n“Demonstration, analysis, and device design considerations for independent DG MOSFETs”
        \nIEEE Transactions on Electron Devices, Vol. 52, Issue 9, September 2005, pp. 2046-2053.<\/p>\n

        G. Curatola, G. Doornbos, J. Loo, Y. V. Ponomarev, G. Iannaccone,
        \n“Detailed modeling of sub- 100-nm MOSFETs based on Schrodinger DD per subband and experiments and evaluation of the performance gap to ballistic transport”
        \nIEEE Transactions on Electron Devices, Vol. 52, Issue 8, August 2005, pp. 1851-1858.<\/p>\n

        D. Munteanu, J. L. Autran, S. Harrison,
        \n“Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics”
        \nJournal of Non-Crystalline Solids, Vol. 351, Issue 21-23, 15 July 2005, pp. 1911-1918.<\/p>\n

        V. D’Alessandro, P. Spirito,
        \n“Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping”
        \nSolid-State Electronics, Vol. 49, Issue 7, July 2005, pp. 1098-1106.<\/p>\n

        A. R. Saha, S. Chattopadhyay, C. Bose, C. K. Maiti,
        \n“Technology CAD of silicided Schottky barrier MOSFET for elevated source-drain engineering”
        \nMaterials Science and Engineering B: Solid-State Materials for Advanced Technology, 2005, Vol. 124-125, pp. 424-430.<\/p>\n

        J. Yuan, J. C. S. Woo,
        \n“A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output”
        \nIEEE Electron Device Letters, Vol. 26, Issue 11, November 2005, pp. 829-831<\/p>\n

        E. J. Preisler, S. Guha, B. R. Perkins, D. Kazazis, A., Zaslavsky,
        \n“Ultrathin epitaxial germanium on crystalline oxide metal-oxide-semiconductor-field-effect transistors”
        \nApplied Physics Letters, Vol. 86, Issue 22, 2005, pp. 1-3.<\/p>\n

        K. Goel, M. Saxena, M. Gupta, R. S. Gupta,
        \n“Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET”
        \nIEEE Transactions on Electron Devices, Vol. 52, Issue 1, January 2005, pp. 23-29.<\/p>\n

        A. Gokirmak, S. Tiwari,
        \n“Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate”
        \nElectronics Letters, Vol. 41, Issue 3, 3 February 2005, pp. 157-158.<\/p>\n

        I. Nam, K. Lee,
        \n“High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology”
        \nIEEE Journal of Solid-State Circuits, Vol. 40, Issue 2, February 2005, pp. 392-402.<\/p>\n

        A. Ohata,
        \n“Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs”
        \nSolid-State Electronics, Vol. 48, Feb. 2004, pp. 345 – 349.<\/p>\n

        S. -E. Tan,
        \n“Velocity saturation in PMOSFET: Using different inversion layer mobility models”
        \n10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys.<\/p>\n

        S. -E. Tan,
        \n“Effects of normal electric field on submicrometer PMOSFET”
        \n10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys.<\/p>\n

        Y. David and U. Efron,
        \n“Design and analysis of an image transceiver device with a low cross-talk level”
        \nIEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings 2004, pp. 41-43.<\/p>\n

        T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba,
        \n“A CMOS-compatible rapid vapor-phase doping process for CMOS scaling”
        \nIEEE Transactions on Electron Devices, Vol. 51, Issue 1, January 2004, pp. 14-19<\/p>\n

        H. Lee, H. Shin, J. Lee,
        \n“Design of a 20 nm T-gate MOSFET with a Source\/Drain-to-Gate Non-Overlapped Structure”
        \nJournal of the Korean Physical Society, Vol. 44, Issue 1, January 2004, pp. 65-68.<\/p>\n

        M. -A. Jaud, S. Barraud, G. Le Carval,
        \n“Impact of quantum mechanical tunneling on off-leakage current in double-gate MOSFET using a quantum drift-diffusion model”
        \n2004 NSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2004 Vol. 2, 2004, pp. 17-20.<\/p>\n

        M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawam K. Ishii, H. Tanoue, K. Sakomoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki,
        \n“Ultrathin Channel Vertical DG MOSFET Fabricated by using Ion-Bombardment-Retarded Etching”
        \nIEEE Trans, Electron Devices, Vol. 51, Dec 2004, pp. 2078-2085.<\/p>\n

        Pascal Scheiblin and Johann Foucher,
        \n“Three-Dimensional Simulation of the Effect of E-Beam Lithography Induced Line-Edge Roughness on N-Type Metal-Oxide Semiconductor Transistor Electrical Characteristics for a 50nm Technology”
        \nJapanese Journal of Applied Physics Vol. 43 No. 6B, 2004, pp. 3838-3842.<\/p>\n

        S. C. Kelly, J. A. Power, M. O’Neill,
        \n“Selection and modeling of integrated RF varactors on a 0.35-\u03bcm BiCMOS technology ”
        \nIEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 2, May, 2004, The International Co.<\/p>\n

        J. Yuan and J. C. S. Woo,
        \n“Nanoscale MOSFET with split-gate design for RF\/analog application”
        \nJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 43, No. 4B, pp. 1742-1745 (2004).<\/p>\n

        E. Gili, V. D. Kunz, C. H. De Groot, T. Uchino, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, P. L. F. Hemment,
        \n“Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance”
        \nSolid-State Electronics, Vol. 48, Issue 4, April 2004, pp. 511-519.<\/p>\n

        N. D. Jankovic and G. A. Armstrong,
        \n“Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers”
        \nMicroelectronics Journal, Vol. 35, Issue 8, August 2004, pp. 647-653.<\/p>\n

        N. G. Gunther, I. I. Pesic, A. A. Mutlu, M. Rahman,
        \n“Modeling C – V characteristics of deep sub-0.1 micron mesoscale MOS devices”
        \nSolid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1883-1890.<\/p>\n

        N. P. Hong, J. -W Hong,
        \n“Charge storage characteristics of SiO2\/Si3N 4 double layer electret”
        \nProceedings of the 2004 IEEE International Conference on Solid Dielectrics ICSD 2004, Vol. 1, Pro.<\/p>\n

        G. Pei, E. C. -C. Kan,
        \n“Independently driven DG MOSFETs for mixed-signal circuits: Part I – Quasi-static and nonquasi-static channel coupling”
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