{"id":31711,"date":"2020-02-26T18:12:34","date_gmt":"2020-02-26T18:12:34","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/interconnect-simulation\/"},"modified":"2020-02-26T18:12:34","modified_gmt":"2020-02-26T18:12:34","slug":"interconnect-simulation","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/tcad-ko\/tcad-published-papers-ko\/interconnect-simulation\/","title":{"rendered":"Interconnect Simulation"},"content":{"rendered":"
\n

Interconnect Simulation<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

Keh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, and Kuo-Cheng Chang,
\n“Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM”,
\nInternational Symposium on VLSI Design, Automation and Test, 2008. VLSI- DAT 2008. IEEE, April 2008, pp. 291 – 294.<\/p>\n

C. Xu, R. Gharpurey, T. S. Fiez, K. Mayaram,
\n“A green function-based parasitic extraction method for inhomogeneous substrate layers”
\nProceedings – Design Automation Conference, 2005, pp. 141-146.<\/p>\n

A.K. Goel, and H. Gopinathannair,
\n“Capacitance extraction for the nanoscale on-chip interconnects”
\nIEEE International Conference on Semiconductor Electronics, Dec 2004, pp. 112- 116.<\/p>\n

C. Renard (SILVACO Data Systems), P. Scheiblin, F. De Crecy, A. Ferron, E. Guichard, P. Holliger, C. Laviron,
\n“Methodology for prediction of ultra shallow junction resistivities considering uncertainties with a genetic algorithm optimization”
\n2004 NSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2004, Vol. 2, 2004 NSTI Nanote.<\/p>\n

D. Lederer, J. -P. Raskin,
\n“Substrate loss mechanisms for microstrip and CPW transmission lines on lossy silicon wafers”
\nSolid-State Electronics, Vol. 47, November 2003, pp. 1927-1936.<\/p>\n

Sheehan DP, Putnam AR, Wright JH,
\n“A solid-state Maxwell demon”
\nFoundations of Physics, 32 (10): 1557-1595 OCT 2002.<\/p>\n

V. Narayanan, Z. Liu, Y. -M. N. Shen, M. Kim, E. C. Kan,
\n“Reduction of metal-semiconductor contact resistance by embedded nanocrystals”
\nTechnical Digest – International Electron Devices Meeting, 2000, pp. 87-89.<\/p>\n

B. Froment, E. Guichard, B. Borot, S. Hanriat, J. Cluzel, J.-P.
\nSchoellkopf, and H. Jaouen,
\n“New interconnect capacitance characterization method for multilevel metal CMOS processes”
\nIEEE International Conference on Interconnect Technology, 1999, pp. 224 – 226.<\/p>\n

S. Putot, F. Charlet, and P. Witomski,
\n“A fast and accurate computation of interconnect capacitance”
\nInternational Electron Device Meeting, Dec. 1999, pp. 893-896.<\/p>\n

D. Salameh and D. Linton,
\n“Study of the effect of various parameters on nonlinear transmission-line (NLTL) performance”
\nIEEE Transactions on Microwave Theory and Techniques, Vol. 47, Issue 3, March 1999, pp. 350 -353.<\/p>\n

Salamh, D. and Linton, D.,
\n“Nonlinear transmission line (NLTL) design as a pulse generator”
\nIEEE High Frequency Postgraduate Student Colloquium, 1996, pp. 7-10.<\/p>\n

Tan, Jilin and Pan, Guang-Wen,
\n“Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses”
\nIEEE Transactions on Components, Packaging & Manufacturing Technology, Part B, August 1996, Vol. 19 Issue 3. pp. 621-627.<\/p>\n<\/div><\/section><\/div>

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