{"id":31705,"date":"2020-02-26T18:36:08","date_gmt":"2020-02-26T18:36:08","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/memory-devices\/"},"modified":"2020-02-26T18:36:08","modified_gmt":"2020-02-26T18:36:08","slug":"memory-devices","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/tcad-ko\/tcad-published-papers-ko\/memory-devices\/","title":{"rendered":"Memory Devices"},"content":{"rendered":"
\n

Memory Devices<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

Daewoong Kang, Hyungcheol Shin,
\n“Improving the cell characteristics using arch-active profile in NAND flash memory having 60 nm design-rule”,
\nSolid-State Electronics, Vol. 54, Issue 11, November 2010, pp. 1263-1268.<\/p>\n

Seongjae Cho, Jung-Dal Choi, Byung-Gook Park, Il Hwan Cho,
\n“Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs”,
\nCurrent Applied Physics, Vol. 10, Issue 4, July 2010, pp. 1096-1102.<\/p>\n

M.A. Garcia-Ramirez, Yoshishige Tsuchiya, Hiroshi Mizuta,
\n“Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell”,
\nMicroelectronic Engineering, Vol. 87, Issues 5-8, May-August 2010, pp. 1284-1286.<\/p>\n

Kyoung-Rok Han, Min-Kyu Jeong, Ilwhan Cho, Jong-Ho Lee,
\n“5-bit\/cell Characteristics using mixed program\/erase mechanism in recessed channel non-volatile memory cells”,
\nCurrent Applied Physics, Vol. 10, Issue 1, Supplement 1, January 2010, pp. e2-e4.<\/p>\n

A. Abdul Aziz, N. Soin,
\n“Dependency of threshold voltage on floating gate and inter-polysilicon dielectric thickness for nonvolatile memory devices”,
\n2010 IEEE International Conference on Semiconductor Electronics (ICSE), 2010, pp. 83 – 87.<\/p>\n

A. Yesayan, N. Chevillon, F. Pr\u00e9galdiny, C. Lallement,
\n“Compact physics-based model for ultrashort FinFETs”,
\n2010 Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2010, pp. 75 – 80.<\/p>\n

Seongjae Cho, Jung Hoon Lee, Shinichi O\u2019uchi, Kazuhiko Endo, Meishoku Masahara, Byung-Gook Park,
\n“Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)”,
\nSolid-State Electronics, Vol. 54, Issue 10, October 2010, pp. 1060-1065.<\/p>\n

M. Moreau, D. Munteanu, J.L. Autran,
\n“Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials”,
\nMicroelectronic Engineering, In Press, Corrected Proof, Available online 6 September 2010.<\/p>\n

M.A. Pavanello, J.A. Martino, E. Simoen, C. Claeys,
\n“Cryogenic operation of FinFETs aiming at analog applications”,
\nCryogenics, Vol. 49, Issue 11, November 2009, pp. 590-594.<\/p>\n

Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park,
\n“3-dimensional terraced NAND (3D TNAND) flash memory-stacked version of folded NAND array”,
\nIEICE Transactions on Electronics, Vol. E92-C, Issue 5, May 2009, pp. 653-658.<\/p>\n

Shin-ichi O\u2019uchi, Kazuhiko Endo, Meishoku Masahara, Kunihiro Sakamoto, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki,
\n“Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology”,
\nSolid-State Electronics, Vol. 52, Issue 11, November 2008, pp. 1694-1702.<\/p>\n

Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park,
\n“Fabrication and characterization of fin SONOS flash memory with separated double-gate structure”,
\nSolid-State Electronics, Vol. 52, Issue 10, October 2008, pp. 1498-1504.<\/p>\n

Mohammad Gh. Mohammad, Kewal K. Saluja,
\n“Analysis and test procedures for NOR flash memory defects”,
\nMicroelectronics Reliability, Vol. 48, Issue 5, May 2008, pp. 698-709.<\/p>\n

P. Magnone, V. Subramanian, B. Parvais, A. Mercha, C. Pace, M. Dehan, S. Decoutere, G. Groeseneken, F. Crupi, S. Pierro,
\n“Gate Vol.tage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices”,
\nMicroelectronic Engineering, Vol. 85, Issue 8, August 2008, pp. 1728-1731.<\/p>\n

A. Kranti, et.al.,
\n“Optimizing FinFET geometry and parasitics for RF applications”,
\nIEEE International SOI Conference, 2008, pp.123-124, Oct. 2008.<\/p>\n

Ismail Saad, Razali Ismail,
\n“Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method”,
\nMicroelectronics Journal, In Press, Corrected Proof, Available online 7 May 2008.<\/p>\n

L. Perniola, J. Razafi ndramora, P. Scheiblin, F. Daug\u00b4e, C. Jahan, B. De Salvo, G. Reimbold, F. Boulanger,
\n“A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures”,
\nCEA-LETI 17, Rue des Martyrs, F – 38054, Grenoble, France, luca.perniola@cea.fr
\nG. Ghibaudo INP Grenoble MINATEC 3, Parvis Louis N\u00b4eel, BP 257, 38016 Grenoble Cedex 1<\/p>\n

S. Jacob\u00a01, 2<\/sup>, L. Perniola1<\/sup>, P. Scheiblin1<\/sup>, B. De Salvo1<\/sup>, G. Lecarval1<\/sup>, E. Jalaguier1<\/sup>, G. Festes2<\/sup>, R. Coppard2<\/sup>, F. Boulanger1<\/sup>, S. Deleonibus1<\/sup>,
\n“TCAD Modeling and Data of NOR Nanocrystal Memories”,
\n1<\/sup>CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, stephanie.jacob@cea.fr
\n2<\/sup>ATMEL Rousset, Zone industrielle, 13790 Rousset, France<\/p>\n

A. Kranti et al.,
\n“Significance of gate underlap architecture in FinFETs for low\u2013Vol.tage Analog\/RF applications”,
\n211th Electrochemical Society Meeting (Chicago, USA), In Proc. ECS Transactions (SOI Device Technology), Vol. 6, Issue 4, pp. 375-380, 2007.<\/p>\n

J. Yu, K. Aflatooni,
\n“Leakage current in DRAM memory cell”,
\n2006 16th Biennial University \/ Goverment \/ Industry Microelectronics Symposium, 2007, pp. 191-194.<\/p>\n

Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Young June Park, Jong-Ho Lee,
\n“Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs) Electron Devices”
\nIEEE Transactions on Vol. 54, Issue 3, March 2007 pp. 537 – 545.<\/p>\n

A. Kranti et al.,
\n“Comparative analysis of nanoscale MOS device architectures for RF applications”,
\nSemiconductor Science and Technology, Vol. 22, No. 5, pp. 481-491, 2007.<\/p>\n

Hiroaki Yamazaki, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka,
\n“Analysis of the subthreshold characteristics for the FC-SGT flash memory cell”,
\nElectronics and Communications in Japan (Part II: Electronics), Vol. 89, Issue 8, August 2006, pp. 34-41.<\/p>\n

Kuk-Hwan KIM, Hyunjin LEE, and Yang-Kyu CHOI,
\n“Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate”
\nIEICE Transaction on Electronics, Vol. E89-C, NO.5 MAY 2006.<\/p>\n

A. Kranti et al.,
\n“Device design considerations for nanoscale double and triple gate FinFETs”,
\nIn Proc. 2005 IEEE SOI Conference, Honolulu, Hawaii, USA, pp. 96-98, 2005.<\/p>\n

R. Duane, M. F. Beug, A. Mathewson,
\n“Novel capacitance coupling coefficient measurement methodology for floating gate nonvolatile memory devices”
\nIEEE Electron Device Letters, Vol. 26, Issue 7, July 2005, pp. 507-509.<\/p>\n

L. Perniola, S. Bernardini, G. Iannaccone, P. Masson, B. De Salvo, G. Ghibaudo, C. Gerardi,
\n“Analytical model of the effects of a nonuniform distribution of stored charge on the electrical characteristics of discrete-trap nonvolatile memories”
\nIEEE Transactions on Nanotechnology, Vol. 4, Issue 3, May 2005, pp. 360-368.<\/p>\n

L. Perniola1,2<\/sup>*, S. Bernardini3<\/sup>, G. Iannaccone1, 6<\/sup>, B. De Salvo\u00a04<\/sup>, G. Ghibaudo2<\/sup>, P. Masson3<\/sup>, C. Gerardi5<\/sup>,
\n“Electrostatic Effect of Localized Charge in Dual Bit Memory Cells with DiscreteTraps”,
\n1<\/sup>Dipartimento di Ingegneria dell\u2019Informazione, Universit\u00e0 degli Studi di Pisa, Via Caruso, 56122 Pisa, Italy, *perniola@enserg.fr
\n2<\/sup>IMEP-CNRS\/INPG, Avenue de Martyrs 32, 38016 Grenoble, France
\n3<\/sup>L2MP-Polytech \u2013 IMT Technop\u00f4le de Ch\u00e2teau Gombert, 13451 Marseille Cedex 20 France
\n4<\/sup>CEA-LETI, Avenue de Martyrs 16, 38054 Grenoble, France
\n5<\/sup>STMicroelectronics, Catania, Italy
\n6<\/sup>IEIIT-CNR, Via Caruso, 56122 Pisa, Italy.<\/p>\n

A. Gorur-Seetharam, C. Lee, E. C. Kan,
\n“The effect of gate geometry on the charging characteristics of metal nanocrystal memories”
\nMaterials Research Society Symposium – Proceedings, Vol. 789, 2003, pp. 71-76.<\/p>\n

M. Hahad, P. Hopper,
\n“High performance semiconductor device simulation on shared memory parallel computers”
\nSISPAD Sept. 2-4, 1996 pp. 137 -138.<\/p>\n

Chimoon Huang and Tahui Wang,
\n“Transient simulation of EPROM writing characteristics, with a novel hot electron injection model”
\nSolid-State Electronics, Vol. 38, Issue 2, February 1995, pp. 461-464.<\/p>\n<\/div><\/section><\/div>

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