{"id":31635,"date":"1998-05-04T16:14:21","date_gmt":"1998-05-04T16:14:21","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/low-power-systems-on-a-chip-cad\/"},"modified":"2021-07-16T22:36:10","modified_gmt":"2021-07-17T05:36:10","slug":"low-power-systems-on-a-chip-cad","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/low-power-systems-on-a-chip-cad\/","title":{"rendered":"Low-Power Systems-on-a-Chip CAD"},"content":{"rendered":"
\n

Low-Power Systems-on-a-Chip CAD<\/h1>\n

E. McShane, Y. Xu, P. Khandelwal, and K. Shenai
\nDepartment of Electrical Engineering & Computer Science, 1135 SED
\nUniversity of Illinois at Chicago,, Chicago, IL 60607<\/i><\/p>\n

Introduction<\/p>\n

Mixed-signal systems-on-a-chip (SOC) integration of digital, analog, RF, and power components is emerging to meet demands for low-power, highly integrated systems in portable computing, wireless communications, and multimedia. Applications are also found in transportation [1] and in aerospace\/defense. Lithography scaling trends are fueling this development, with RF performance now possible from bulk CMOS. Deep submicron devices, however, are increasingly sensitive to second-order effects with the result that traditional circuit simulations cannot accurately predict performance without first accounting for specific device structures and layout topography. The complex interaction between digital switching logic and analog or RF continuous wave circuits further complicates simulation and modeling. Described below are the tools necessary for SOC design and modeling, as well as two applications examples based on research being conducted at the Systems on Silicon Research Center (SYSREC) at the University of Illinois at Chicago (UIC).<\/p>\n<\/div><\/section><\/div>

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