{"id":31614,"date":"1998-08-01T15:14:49","date_gmt":"1998-08-01T15:14:49","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/simulating-accurate-3d-geometries-for-interconnect-parasitic-extraction-using-clever\/"},"modified":"2021-07-16T22:35:15","modified_gmt":"2021-07-17T05:35:15","slug":"simulating-accurate-3d-geometries-for-interconnect-parasitic-extraction-using-clever","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/simulating-accurate-3d-geometries-for-interconnect-parasitic-extraction-using-clever\/","title":{"rendered":"Simulating Accurate 3D Geometries for Interconnect Parasitic Extraction Using CLEVER"},"content":{"rendered":"
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Simulating Accurate 3D Geometries for Interconnect Parasitic Extraction Using CLEVER<\/h1>\n

Introduction<\/p>\n

CLEVER<\/b>\u00a0is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process simulator is used to realisticly reproduce the effects of photolithography, deposition and etching on the resulting structure topography. Geometric etches and depositions are also possible to increase the speed of simulation if required. The process steps are driven from existing masks in standard GDSII data format from the actual design, or the mask set may be created using\u00a0MaskViews<\/b>\u00a0. The 3D grid re-meshing required for each of the steps is generated totally automatically and requires no user input. This feature makes the whole package exceptionally easy to use, even for those unfamiliar with process simulation. Figure 1 shows an SRAM cell geometry during processing. Effects of lithography on the metal 1 layer are seen.<\/p>\n<\/div><\/section><\/div>

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