{"id":31587,"date":"1998-11-01T16:34:46","date_gmt":"1998-11-02T00:34:46","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/validation-of-clever-interconnect-parasitics-with-0-18-%c2%b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\/"},"modified":"2026-10-15T14:43:39","modified_gmt":"2026-10-15T21:43:39","slug":"validation-of-clever-interconnect-parasitics-with-0-18-%c2%b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/analog-custom-design-ko\/parasiticsnetlist-ko\/validation-of-clever-interconnect-parasitics-with-0-18-%c2%b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\/","title":{"rendered":"Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements Benoit Froment and Herve Jaouen &#8211; SGS-Thomson Microelectronics"},"content":{"rendered":"<h1>Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements <i>Benoit Froment and Herve Jaouen-SGS-Thomson Microelectronics<\/i><\/h1>\n<p class=\"feature\">Motivation<\/p>\n<p><b>CLEVER<\/b>\u00a0can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of\u00a0<b>CLEVER<\/b>\u00a0results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator. Validation was done for a state-of-the-art process applicable to 0.18 \u00b5m technology. The process has the following features:<\/p>\n<ul class=\"regular3\">\n<li>multiple dielectrics<\/li>\n<li>conformal deposition around conductors<\/li>\n<li>inter-metal fill with low-k dielectric<\/li>\n<li><span class=\"regular\">non rectangular metal cross sections<\/span><\/li>\n<\/ul>\n<p class=\"feature\">Process Description<\/p>\n<p>The aim of the validation exercise is to make comparison of simulated and measured capacitances. To achieve this it is necessary to be very precise in the description of the process steps. The capacitances for deep sub-micron structures are highly dependent on process geometry especially for multi-dielectric technologies.\u00a0<b>CLEVER<\/b>\u00a0was used since it is designed to model interconnect parasitics by simulating the 3D back end process in a very accurate manner due to its advanced process models for photolithography deposition and etching [1].<\/p>\n<p>The measurements and\u00a0<b>CLEVER<\/b>\u00a0simulations were carried out with the ST HCMOS7X process. The pitch is 1um and the part of SiO2 usually deposited by plasma (ECR), is replaced by a low-k material gapfill (Fox). The Fox thickness target is around 600nm. The permittivity of Fox deposited between metal line is around 3, whereas the dielectric constant of the TEOS capping layer is 4.2. However, there is a slight variation on these values due to the process dispersion. It is assumed that these fluctuations are under 5% of the initial value.<\/p>\n<p><img loading=\"lazy\" width=\"1202\" height=\"1669\" src=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1.jpg\" class=\"cleaned-enfold-image\" alt=\"\" decoding=\"async\" loading=\"lazy\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1.jpg 1202w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-216x300.jpg 216w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-742x1030.jpg 742w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-768x1066.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-1106x1536.jpg 1106w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-1080x1500.jpg 1080w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-508x705.jpg 508w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-27x37.jpg 27w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-40x55.jpg 40w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1-35x48.jpg 35w\" sizes=\"auto, (max-width: 1202px) 100vw, 1202px\" \/><\/p>\n<p><a href=\"https:\/\/silvaco.com\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=download&#038;nm=simstd_nov_1998_a1.pdf\" class=\"BGT-btn\" target=\"_blank\" rel=\"noopener noreferrer\">Download Simulation Standard<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>CLEVER\u00a0can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of\u00a0CLEVER\u00a0results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator.<\/p>\n","protected":false},"author":12,"featured_media":22236,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7485,7486],"tags":[7875],"class_list":["post-31587","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-parasiticsnetlist-ko","category-simulation-standard-ko","tag-tcad-2-ko","entry","has-media"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.7 (Yoast SEO v28.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements Benoit Froment and Herve Jaouen - SGS-Thomson Microelectronics - Silvaco<\/title>\n<meta name=\"description\" content=\"CLEVER\u00a0can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of\u00a0CLEVER\u00a0results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/ko\/analog-custom-design-ko\/parasiticsnetlist-ko\/validation-of-clever-interconnect-parasitics-with-0-18-\u00b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\/\" \/>\n<meta property=\"og:locale\" content=\"ko_KR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements Benoit Froment and Herve Jaouen - SGS-Thomson Microelectronics\" \/>\n<meta property=\"og:description\" content=\"CLEVER\u00a0can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of\u00a0CLEVER\u00a0results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/ko\/analog-custom-design-ko\/parasiticsnetlist-ko\/validation-of-clever-interconnect-parasitics-with-0-18-\u00b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"1998-11-02T00:34:46+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-10-15T21:43:39+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_1998_a1.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1202\" \/>\n\t<meta property=\"og:image:height\" content=\"1669\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Casey Molver\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\uae00\uc4f4\uc774\" \/>\n\t<meta name=\"twitter:data1\" content=\"Casey Molver\" \/>\n\t<meta name=\"twitter:label2\" content=\"\uc608\uc0c1 \ub418\ub294 \ud310\ub3c5 \uc2dc\uac04\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ko\\\/analog-custom-design-ko\\\/parasiticsnetlist-ko\\\/validation-of-clever-interconnect-parasitics-with-0-18-%c2%b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ko\\\/analog-custom-design-ko\\\/parasiticsnetlist-ko\\\/validation-of-clever-interconnect-parasitics-with-0-18-%c2%b5m-process-measurements-benoit-froment-and-herve-jaouen-sgs-thomson-microelectronics\\\/\"},\"author\":{\"name\":\"Casey Molver\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/#\\\/schema\\\/person\\\/2763eb741ca5ac04477fdff50ed84c80\"},\"headline\":\"Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements Benoit Froment and Herve Jaouen &#8211; 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