{"id":31538,"date":"1999-05-03T17:18:02","date_gmt":"1999-05-03T17:18:02","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/circuit-performance-analysis-of-multiple-athena-transistors-using-mixedmode\/"},"modified":"2021-07-16T22:15:09","modified_gmt":"2021-07-17T05:15:09","slug":"circuit-performance-analysis-of-multiple-athena-transistors-using-mixedmode","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/circuit-performance-analysis-of-multiple-athena-transistors-using-mixedmode\/","title":{"rendered":"Circuit Performance Analysis of Multiple ATHENA Transistors Using MixedMode"},"content":{"rendered":"
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Circuit Performance Analysis of Multiple\u00a0ATHENA<\/i>\u00a0Transistors Using\u00a0MixedMode<\/i><\/h1>\n

Introduction<\/p>\n

In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using\u00a0ATLAS<\/i><\/b>\/MixedMode<\/i><\/b>\u00a0was introduced. The MOSFETs used in the\u00a0MixedMode<\/i><\/b>\u00a0simulation were created using analytical doping profiles specified within\u00a0ATLAS<\/i><\/b>. This article is intended to investigate some of the effects of process variation on ring oscillator performance. Thus, the individual devices in the ring oscillator circuit are created usingthe two-dimensional process simulation program,\u00a0ATHENA<\/i><\/b>.<\/p>\n

Simulation Methodology<\/p>\n

Figure 1 pictorially presents the simulation methodology used in this work. NMOS and PMOS devices were separately created in\u00a0ATHENA<\/i><\/b>, where process conditions were specified (e.g., oxidation times and temperatures, etc. ) and related process information was extracted (e.g., gate oxide thicknesses). The resulting NMOS and PMOS device structures were remeshed using DevEdit to concentrate the mesh in the inversion region and in regions where the doping concentration varied spatially. This structure remeshing provided a reduced node count for each device and a sufficient mesh for device simulation. The ring oscillator circuit (shown in Figure 2) was defined as it was in Part I [1], and the NMOS and PMOS transistors from the process simulation were used for each inverter in the circuit. As in Part I a piecewise linear waveform is applied to the supply voltage, causing the circuit to begin oscillating. Transient analysis is carried out for 500 picoseconds, and the gate delay is extracted from the voltage versus time waveforms according to equation 1 in Part I. The simulation scheme is automated using the\u00a0VWF Automation Tools<\/i><\/b>.<\/p>\n<\/div><\/section><\/div>

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