{"id":31296,"date":"2003-01-01T22:53:54","date_gmt":"2003-01-01T22:53:54","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/behavioral-modeling-and-simulation-in-the-scholar-schematic-environment\/"},"modified":"2021-07-16T22:00:40","modified_gmt":"2021-07-17T05:00:40","slug":"behavioral-modeling-and-simulation-in-the-scholar-schematic-environment","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/behavioral-modeling-and-simulation-in-the-scholar-schematic-environment\/","title":{"rendered":"Behavioral Modeling and Simulation in the Scholar Schematic Environment"},"content":{"rendered":"
\n

Behavioral Modeling and Simulation in the Scholar Schematic Environment<\/h1>\n

Introduction<\/h3>\n

This article focusses on the use of Silvaco International\u2019s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is a standard language used for behavioral level modeling. Verilog A combined with Scholar forms a powerful tool capable of running both schematics with Verilog A modules and mixed Verilog A and physical model simulations. Verilog A may also be used in an environment for compact model development but primarily it is used to reduce schematics of significant amounts of transistors into efficient maintainable and changeable blocks which can be instantiated on any level of a design.<\/p>\n<\/div><\/section><\/div>

<\/div>