{"id":31288,"date":"2003-02-01T20:20:37","date_gmt":"2003-02-01T20:20:37","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/the-importance-of-mesh-definition-in-strained-si-heterostructure-simulation\/"},"modified":"2021-07-16T22:00:25","modified_gmt":"2021-07-17T05:00:25","slug":"the-importance-of-mesh-definition-in-strained-si-heterostructure-simulation","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/the-importance-of-mesh-definition-in-strained-si-heterostructure-simulation\/","title":{"rendered":"The Importance of Mesh Definition in Strained-Si Heterostructure Simulation"},"content":{"rendered":"
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The Importance of Mesh Definition in Strained-Si Heterostructure Simulation<\/h1>\n

Introduction<\/h3>\n

Computer simulation is used extensively to verify physical phenomena in semiconductor devices. Meshing plays an essential role in obtaining good simulation results. If care is not properly taken, serious errors may occur in the results. The objective of this article is to identify errors in the simulation of the strained-Si heterostructure MOSFET device using\u00a0ATLAS<\/i><\/b>, Silvaco\u2019s two-dimensional numerical simulator.<\/p>\n

Simulation Structure<\/h3>\n

Many research groups have extensively investigated Si\/SiGe heterostructure MOSFETs in recent years [1, 2]. In these structures, a Si channel is grown under tensile strain between relaxed SiGe layers. The strain induced conduction band offset at the Si\/SiGe heterointerface leads to the formation of a two-dimensional electron gas in the strained Si layer that substantially enhances electron mobility in bulk silicon. Si\/SiGe heterostructure MOSFETs therefore deomonsterate excellent device performance.<\/p>\n

The strained-Si p-channel heterostructure MOSFET is modeled for this article with\u00a0ATLAS<\/i><\/b>, Silvaco\u2019s the two-dimensional numerical simulator, in order to study the effect of meshing on the simulation results, shown in Figure 1.<\/p>\n

The structure consists of a 0.5\u00b5m strained-Si p-MOSFET. A thin strained graded Si1-x<\/sub>Gex (110\u00c5) buffer cap is sandwiched between the strained-Si layer (70\u00c5) and relaxed Si1-x<\/sub>Gex<\/sub>\u00a0layer (0.402\u00b5m). This helps the user avoid the problem of hole confinement at the strained-Si\/SiGe interface as the Ge grading reduces valence band discontinuity (Figure 2).<\/p>\n<\/div><\/section><\/div>

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