{"id":31157,"date":"2004-05-01T00:07:57","date_gmt":"2004-05-01T00:07:57","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/lpe-optimization-with-clever-hipex-exact-linkage-methodology\/"},"modified":"2021-07-16T21:53:14","modified_gmt":"2021-07-17T04:53:14","slug":"lpe-optimization-with-clever-hipex-exact-linkage-methodology","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/lpe-optimization-with-clever-hipex-exact-linkage-methodology\/","title":{"rendered":"LPE Optimization with Clever\/Hipex\/Exact Linkage Methodology"},"content":{"rendered":"
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LPE Optimization with\u00a0Clever\/Hipex\/Exact <\/em>Linkage Methodology<\/h1>\n

1. Introduction<\/strong><\/p>\n

On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower. The quantitative consideration of coupling capacitance based on three-dimensional calculation is indispensable. Conventional advanced LSI design tools and methodology are limited in their ability to optimize the LPE library. As a result, the discussion of LPE tool accuracy and extracted parasitic results lack significant quantitative generality.<\/p>\n

This article proposes a new methodology for verifying accuracy of LPE tools and optimizing the LPE library for today\u2019s 0.13 um designs and the more scaled-down next generation LSI design of nodes at 100 nm or less.<\/p>\n

2. Simulation Flow and Methodology<\/strong><\/p>\n

Figure 1 is a LPE optimization simulation flow that links Silvaco\u2019s\u00a0CLEVER, HIPEX<\/em><\/strong>, and\u00a0EXACT<\/em><\/strong>\u00a0tools. The process includes four distinct stages.<\/p>\n