{"id":31156,"date":"2004-05-01T00:10:09","date_gmt":"2004-05-01T00:10:09","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/stellar-process-based-parasitics-capacitance-extraction-on-large-custom-cells\/"},"modified":"2021-07-16T21:53:13","modified_gmt":"2021-07-17T04:53:13","slug":"stellar-process-based-parasitics-capacitance-extraction-on-large-custom-cells","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/stellar-process-based-parasitics-capacitance-extraction-on-large-custom-cells\/","title":{"rendered":"STELLAR \u2013 Process Based Parasitics Capacitance Extraction on Large Custom Cells"},"content":{"rendered":"
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STELLAR \u2013 Process Based Parasitics Capacitance Extraction on Large Custom Cells : Overview and Features<\/h1>\n

I Introduction<\/strong><\/p>\n

SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design. Indeed based on the success of\u00a0CLEVER<\/em><\/strong>\u00a0and\u00a0EXACT<\/strong><\/em>, SILVACO wants to provide to customers tools with the same accuracy as the previous ones but dedicated to bigger layouts. It is becoming increasingly clear that with current designs around 0.1um parasitics are more and more important to take into account. Designers have to make an important decision whether to have verification either very precise using tools like\u00a0CLEVER<\/strong><\/em>\u00a0on relatively small layouts [1] or using classical LPE tool like\u00a0HIPEX<\/em><\/strong>\u00a0[2] which are known to be sometimes not accurate enough. Between them a wide gap lies and the aim of SILVACO new products is to fill it. These new tools keep the same famous in-house trends so-called TCAD driven CAD which means that as a fundamental core a 3D process simulator and a 3D field solver are the basis for an accurate parasitics extraction today.<\/p>\n

This article will illustrate the architecture and the applications of\u00a0STELLAR<\/em><\/strong>\u00a0our new Fast Capacitance Parasitics Extractor Software and we will compare results to the field solver reference on the market\u00a0CLEVER<\/em><\/strong>.<\/p>\n

II STELLAR Architecture<\/strong><\/p>\n

Parasitic extraction accuracy is crucial for deep submicron designs. The targeted accuracy has been considered to be 3D Field Solver based.\u00a0STELLAR<\/em><\/strong>\u00a0reaches this goal by using a combination of 3D process and 3D field solver capabilities. The 3D process simulation allows the geometry of the final structure to be very accurately generated. Once the geometry is generated, a 3D topology of the layout is obtained. This is essential for accurate parasitic extraction for deep and ultra deep submicron technology.<\/p>\n

This combination also allows\u00a0STELLAR<\/em><\/strong>\u00a0to be a powerful and flexible solution for extracting highly accurate parasitic capacitances in deep submicron designs summarized in the following chart. Note the architecture of\u00a0STELLAR<\/em><\/strong>\u00a0(Figure 1) is identical to that of\u00a0CLEVER<\/strong><\/em>\u00a0and\u00a0QUEST<\/em><\/strong>. However the process simulator and the field solver are different.<\/p>\n<\/div><\/section><\/div>

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