{"id":30907,"date":"2012-01-01T17:28:53","date_gmt":"2012-01-01T17:28:53","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/simulation-of-stresses-and-mobility-enhancement-factors-in-3d-inverter-cell\/"},"modified":"2021-07-16T21:43:02","modified_gmt":"2021-07-17T04:43:02","slug":"simulation-of-stresses-and-mobility-enhancement-factors-in-3d-inverter-cell","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/simulation-standard-ko\/simulation-of-stresses-and-mobility-enhancement-factors-in-3d-inverter-cell\/","title":{"rendered":"Simulation of Stresses and Mobility Enhancement Factors in 3D Inverter Cell"},"content":{"rendered":"
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Simulation of Stresses and Mobility Enhancement Factors in 3D Inverter Cell<\/h1>\n

Introduction<\/strong><\/p>\n

The analysis and characterization of stress effects have become an integral part of semiconductor technology and device design. In a typical semiconductor process flow the stresses are generated primarily due to volume expansion or contraction of the adjacent materials during temperature variations. Stresses could also be generated during oxidation, silicidation, etching, and deposition processes or due to lattice expansion or contraction after introducing large doses of dopants. Simulation of process induced stresses is an important component of traditional TCAD analysis since these stresses could have adverse or positive effect on individual process steps or on final device characteristics.<\/p>\n

It is even more important to accurately simulate and optimize so-called stress engineering processes. Stress engineering is a deliberate introduction of stresses into device structures with a goal to enhance carrier mobility and consequently device performance. The most common method of introducing desirable stresses into a transistor channel region is deposition of high tensile or high compressive films of nitride type materials [1]. This method is called the global stress engineering. Another method introduces stresses by formation of locally strained source\/drain regions [2-5]. These local regions could be created, for example, by epitaxial growth of compositional Si:Ge or Si:C materials.<\/p>\n

In this paper we use 3D simulator VICTORY Stress to analyze stress effects on carrier mobilities of individual n-FinFET and p-FinFET devices as well as on characteristics of an inverter cell consisting of one n-FinFET and two p-FinFETs. The stresses in a whole cell are analyzed in this paper for the first time. Typically stress simulations have been preformed just in separate devices. However, it appears that proximity effects may require simulation of the whole cell. Both global and local methods of stress engineering are considered for each device type.<\/p>\n<\/div><\/section><\/div>

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