{"id":28237,"date":"2019-07-02T14:43:48","date_gmt":"2019-07-02T14:43:48","guid":{"rendered":"https:\/\/silvaco.com\/%eb%b6%84%eb%a5%98%eb%90%98%ec%a7%80-%ec%95%8a%ec%9d%8c\/talking-atoms-to-systems-in-next-generation-soc-designs\/"},"modified":"2019-07-02T14:43:48","modified_gmt":"2019-07-02T14:43:48","slug":"talking-atoms-to-systems-in-next-generation-soc-designs","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ko\/tcad-ko\/tcad-blogs-ko\/talking-atoms-to-systems-in-next-generation-soc-designs\/","title":{"rendered":"Talking Atoms to Systems in Next-Generation SoC Designs"},"content":{"rendered":"
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Taking Atoms to Systems in Next-Generation SoC Designs<\/h1>\n

\"\"New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.<\/p>\n

Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West<\/a>, co-located with SEMICON West<\/a>, July 9-11 at the Moscone Center in San Francisco.<\/p>\n

ESD Alliance: For years now, the assumption is that each new chip design is more complex than the last. Why are the latest SoC designs even more complex than before?<\/strong><\/p>\n

Taheri:<\/strong> New SoC devices for mobile phones, automobiles, intelligent edge nodes, big data compute and storage are adopting artificial intelligence and machine learning technologies. This is driving new compute, data flow, as well as memory architectures that are bandwidth-limited and some require photonic interfaces.<\/p>\n

One common denominator in present SoC design are the numerous blocks of IP. On average, over 85% of these blocks are reused. It\u2019s cost-prohibitive to make these chips over and over again with new IP. According to some estimates, 90% of IP used in an SoC design by 2025 will be reused \u2013 only 10% is new technologies. That 10% is significant.<\/p>\n

ESD Alliance: How so?<\/strong><\/p>\n

Taheri:<\/strong> Complex new technologies including flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs such as NVIDIA\u2019s Xavier and Apple\u2019s A12 use and reuse design IP at the architectural level.<\/p>\n

New technologies mean new materials and new processes. Single nanometer process nodes require specialized new IP that needs to be simulated and analyzed down to the nanometer and atomic levels.<\/p>\n

ESD Alliance: Does the atomic level changes the design equation?<\/strong><\/p>\n

Taheri:<\/strong> Yes, it does. Designers need to be able to simulate at the atomic level and understand properties of these materials, and how they behave in at-process and at-device levels. They need be able to simulate the material’s nanometer geometries, how molecules behave and how they interact for device operations. When they put together a process and a device, they need to know how the pieces behave and simulate before production.<\/p>\n

In other words, they run quite a few design experiments and quite a bit of simulation before they finalize the circuits and devices to silicon to save money.<\/p>\n

ESD Alliance:<\/strong> It\u2019s obvious design automation will continue to have a vital role in design.<\/p>\n

Taheri:<\/strong> Yes, absolutely. Design technology co-optimization (DTCO) using TCAD solutions and proven design IP are needed to address the span from architecture to device and process physics.<\/p>\n

The importance of simulation, emulation and design technology co-optimization, along with fully verified and proven IP for SoC design, cannot be overstated. As designers generate devices and processors, they take that up to circuit-level simulation and high-level simulation, schematic capture, extractions and back annotation. They can go from atoms to simulating systems to the ability to do that under the same umbrella in order to get better chips, better yield and lower cost.<\/p>\n

Taheri\u2019s talk Next Generation of SoC Design: From Atoms to Systems will be part of the Meet the Experts More than Moore<\/a> session Tuesday, July 9, at 11:30 a.m. at the ES Design West<\/a> SMART Design Pavilion. SEMICON West<\/a> attendees are invited to Moscone Center\u2019s South Hall to learn more about electronic system and semiconductor design and its links to the electronic product manufacturing and supply chain.<\/p>\n

Register<\/strong><\/a> for ES Design West or SEMICON West.<\/p>\n<\/div><\/section><\/div>

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