“We’ve been working with Silvaco since we started the company 13 years ago. They’ve been a big part of our success. As of today, we’re still using their Expert tool for the layout editor. All of our designs are done in Expert all the way down to 5 nanometer.” In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for nanometer IC design success.\u00a0 He talks about using a suite of Silvaco design tools down to the latest 5 nm silicon process nodes. A full ranscript of the conversation is below, as well.<\/span><\/p>\n GB<\/strong>: Randy, we were talking a little bit off camera about all the new nanometer process nodes and Silicon Creations works with quite a number of them. What are you working at as [for the] leading edge these days? <\/span><\/p>\n RC<\/strong>: Good question. Actually, there are quite a few advanced process nodes these days that are creating a lot of interesting challenges for the IP providers and designers of hard macro circuitry. Of course, TSMC is kind of in the lead. We’ve got their 16 nm and 12 nm FinFET nodes that are already in stable production. In the past year, we saw 7 nm ramping to mass production and now, we already have 5 nm silicon back. Of course, each one of these nodes has increasing demands for simulation speed, for verification mismatch, reliability and so on.\u00a0 At the same time, we’ve got GlobalFoundries and Samsung coming out with a very compelling offerings in FinFET as well, Samsung in 10 and 8 nm, and 7 nm now. They’re even talking about going to the next generation after that, so this is quite a challenge. Each IP has to be fully redesigned, fully re-verified. The amount of tools involved to do all of that is also quite a challenge to keep costs low.<\/span><\/p>\n GB<\/strong>: Well, how many tape-outs did you do last year? <\/span><\/p>\n RC<\/strong>: In total, we had about 100 tape-outs among all of our customers. So we’re taping out… One of our customers is taping out roughly two times every week.<\/span><\/p>\n GB<\/strong>: So that means you’re doing a lot of simulation 24 hours a day. How many machines do you have in your server farm? <\/span><\/p>\n RC<\/strong>: Actually on our server farm, we have about 2400 CPUs, it all runs locally. Actually, one of our biggest costs has become air conditioning, trying to pull all the heat out of these server farms. We’ve got multiple EDA vendors that we use simulation licenses for, and a whole host of verification tools in order to properly sign off on these complex designs.<\/span><\/p>\n RC<\/strong>: Now, Silvaco is a part of your tool mix. What tools do you use from Silvaco to work at these leading nanometer nodes? <\/span><\/p>\n RC<\/strong>: Yeah, we’ve been working with Silvaco since we started the company 13 years ago. They’ve been a big part of our success. As of today, we’re still using their Expert tool for the layout editor. All of our designs are done in Expert all the way down to 5 nanometer. This has been a critical part of our ability to quickly move between all of these different process nodes that I had mentioned. It allows us to easily write our own P-cells, write our own layout rules, write our own scripts for modifying. For example, we use scripts in Expert to quickly go from TSMC 7FF to 7FF+. We don’t have to have any outside EDA or flow for that. We also use the Gateway Schematic Editor and then in the backend, we’re using SmartSpace for simulation and Silos for Verilog simulation.<\/span><\/p>\n GB<\/strong>: Randy, thanks for bringing us up to date about all the exciting things happening at Silicon Creations.<\/span><\/p>\n RC<\/strong>: You’re very welcome. Thank you for having me.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":" In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for nanometer IC design success. He talks about using a suite of Silvaco design tools down to the latest 5 nm silicon process nodes. A full ranscript of the conversation is below, as well.<\/p>\n","protected":false},"author":12,"featured_media":20256,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7610],"tags":[],"class_list":["post-28207","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-custom-blogs-ko","entry","has-media"],"yoast_head":"\n
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