HIPEX-Net: Hierarchical Layout Extractor for Expert Editor


HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted netlist. This checks for connectivity errors in a chip design such as opens, shorts, and dangling nodes.

HIPEX-Net is a sophisticated script-driven tool. To invoke the extraction, the user must provide a number of input script files in LISA: Language for Interfacing Silvaco Applications. These are option file, layer mapping files, and technology file. HIPEX-Net technology is defined by a list of various LISA statements that build derived layers, connectivity, and devices. However, the input generation is easy when running HIPEX-Net from Expert.

Expert automatically creates all the input files needed by HIPEX-Net. You use the Expert GUI to define technology and the extractor settings rather than writing LISA scripts manually. You can also use Dracula technology converter Expert provides.

HIPEX-Net introduces in Expert hierarchical Node Probing feature.