A Comparison Between Classical Full Chip Extraction and Field Solver Parasitic Extraction

Introduction

With current technologies, parasitic effects must be taken into account in the first phase of IC design development. So, Layout Parasitic Extraction (LPE) is today a very important step before circuit simulation and tape out.

This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC based on geometrical information, then using a field solver based extraction tool CLEVER.

The HIPEX-RC and CLEVER core features will be detailed in the first part. We will then use these two different tools to characterize inverters and see the consequences on parasitics extraction accuracy.

The goal of this article is not to give exhaustive information about the software but to highlight the differences in regards to capacitance extraction.