• Jivaro

Jivaro – Parasitic Reduction

Accelerate Your SPICE Simulations

Jivaro is a unique stand-alone solution dedicated to the reduction of parasitic networks. Jivaro helps back-end verification teams speed up post-layout SPICE simulation of huge extracted parasitic circuits, while maintaining high accuracy.

Jivaro has been proven to accelerate circuit simulation up to 15X faster while preserving high accuracy. Leading IDM and fabless companies worldwide have adopted Jivaro to address the challenges of parasitic reduction for technology nodes from 65nm down to 5nm. Jivaro applies a patented mathematical approach to perform Model Order Reduction (MOR) to reduce parasitic complexity. In contrast to rules-based methods, Jivaro allows designers to tradeoff between accuracy and reduction, with the user controlling the benefits.

Jivaro Reduction Flow

Jivaro has no dependencies on the extraction and simulation tools utilized and can plug directly into any design flow. It allows complete adaptability to the flow and the type of designs or challenges, providing a single solution for all cases.

There are over 30 parameters that enable broad control over speed and accuracy results. To enable fast implementation and ease of use, Jivaro also provides an Automatic Mode capability that adapts and optimizes to your design environment.

Different reduction thresholds may be applied to different parts of the design to optimize reduction. In addition to Model Order Reduction (MOR) Jivaro also provides reduction of the number of active devices, and can deal with all netlist types, including power nets.

Jivaro SPICE Simulation Acceleration

Features

  • Accepts R, RC, RCC, RLC, RLCK, controlled sources
  • Supports DSPF, SPEF, SPICE3, HSPICE®, SPECTRE®, Calibre® View, OA databases
  • Reduces temperature-dependent parasitic networks and multi-corner extracted netlists
  • Can be applied differently on selected nets, sub-circuits or paths within the hierarchy
  • Merges multi-finger active devices
  • Supports negative resistors
  • Graphical user interface to pilot the reduction options or inline binaries for batch runs
  • Compatible with all major EDA tools

Benefits

  • Up to 15X post-layout SPICE simulations speedup
  • Maintains accuracy to <1%
  • Enables the largest or impossible simulations
  • Enables including power nets and metal fills in simulation for more accuracy
  • Easy plug-and-play into existing flow using Auto Mode
  • Allows for customization of reduction strategy to meet verification objectives