Q: What Types of 3D Delaunay Shape Refinement can be used in Victory Process?A. The Victory Process cell mode Delaunay 3D device meshing algorithm already includes various TCAD-based local refinement algorithms to ensure accurate and robust device simulation. These include junction and interface distance refinement. One benefit of these approaches is that complex refinement behavior can be specified via a simple deck interface, but a limitation is that the results can only vary according to the small number of parameters of the schemes. In some cases, such as particle path refinement, it can be useful to have finer, more local control over the mesh and the shape distance refinement schemes have been produced to support this.

The flat panel device for active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diode displays (AMOLEDs) has utilized a low cost amorphous silicon or low temperature poly-silicon (LTPS) as a fast switching transistor in mobile devices,TVs, and other display consumer electronics. Recently, amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) is now one of the most important materials in the display area for flexibility, large-area uniformity and high mobility. The conventional a-Si:H TFT or LTPS devices have many degradation problems such as bias stress and photo induced instabilities that are the most important factors which must be fully understood and analyzed to improve the device design. These instabilities come from time-dependent density of states (DOS) change in forbidden band gap of material during device operation.

The NAND Flash memory cell has been refined to reduce the bit cost, but the limit of its miniaturization has been reached due to the high electric field problem and the difficulty of lithography. On that account, three-dimensional stack cell structures have been adopted to achieve mass storage devices [1-3]. It has already been reported that the fabrication of 256Gbit NAND Flash memory with 48 stacked layers started on August in 2015 [4, 5]. For the fabrication of the stack structures, it is necessary to realize etching of deep holes. For examples, if using 30nm design rules and one layer thickness is 40nm, its depth becomes 1.92um. If the holes diameter is 100 nm, its aspect ratio becomes 19.2. Then, in the next generation, the 512 Gbit flash memory cell will need the deep hole with the aspect ratio of 38.4 for 3.84um-depth. For investigating more suitable process conditions or optimum etched topography, accurate three-dimensional etching simulation is required, but it takes a very long time to simulate this deep hole etching accurately if using usual simulation methods like the Monte-Carlo method, because the aspect ratio of this deep hole is very large and therefore, the flux calculation effort of enhancing ions and neutral radical species is enourmous for a reactive enhanced ion etching (RIE) model.