엔트리 Ingrid Schwarz

Touch Panel Capacitance Extraction in Hipex Full Chip Extraction Tool Using Stellar Field Solver

The previously standalone Stellar GUI based field solver tool for parasitic extraction is now integrated into Hipex (Silvaco’s full chip extraction tool) in Expert GUI. In Hipex, user can choose proper extraction method (including Steller solver) among different approaches. The GUI of Expert (Silvaco’s layout editor) has been extended to provide technology setup for Stellar mode of Hipex. Also, Expert provides full functional features of GDS drawing, editing and rule checking. As opposed to the Clever field solver based on adaptive meshing, Stellar can handle very large layout size with less memory and reduced runtime with acceptable accuracy (as compared to Clever). Clever, as very accurate adaptive meshing field solver, can be used as reference accuracy check when Stellar or rule based parasitic extraction method is performed in Hipex. In this article, we will review the basic interface of Hipex in Expert GUI using Stellar as a field solver to extract capacitance in touch panel example.

Dynamic Analysis of Liquid Crystal Pixels

We have demonstrated in previous articles the static electrical and optical simulation of LC cells [1][2]. The last piece of the function for a comprehensive analysis of an LC pixel is the capability of performing transient simulation. In this article, we will show the dynamic calculation of the LC director and the combination of electrical and optical simulation.

VarMan을 사용한 메모리 통계 특성화 솔루션

2018년 9월 21일 | 2:00am-2:30am (한국 시각)
VarMan은 Variability eXplorer, 하이-시그마 Yield Estimation, 하이-시그마 Performance Limit, eXtreme Memory Analysis 등을 포함합니다. 높은 정확성을 유지하면서도 메모리 특성화와 품질 보증에 필요한 시뮬레이션 횟수를 크게 줄여, 변동성이 존재하는 상태에서 설계와 특성화를 구현합니다.

FPD 설계의 생산성 향상

2018년 8월 22일 | 3:00am-3:30am (한국 시각)
이번 시간에 FPD 레이아웃의 설계 생산성을 높이기 위한 실바코의 레이아웃 에디터, Expert의 새로운 기능을 소개합니다.

An Empirical Composition Dependent Model of Dopant Diffusion Coefficients in Si, Si1-x Gex and Ge Material Systems

Previously published fast empirical models for diffusion coefficients in silicon-germanium (Si1-x Gex) [1][2] were not applicable to high germanium content x≥0.5 and hence did not properly extend towards germanium. For some dopants, diffusion coefficients become very small and hence this model cannot be applied to devices containing silicon-germanium with high germanium content or devices containing silicon, silicon-germanium and germanium

TCAD Simulation of Leakage Through Threading Dislocations in GaN-based pn-diodes

Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].