엔트리 Ingrid Schwarz

BSIM3SOI Level=25 Model Released in SmartSpice

The Berkeley BSIM3SOI model, released in December 1997, is now available within SmartSpice as the MOSFET level=25 model. This model incorporates three separate implementations: the original Berkeley model implementation is invoked with the selector Berk=2; the Silvaco implementation is invoked with Berk=-2.

Savage Enhanced with Recognition and Reporting of Hierarchical Structure of Errors

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension of capabilities of flat DRC systems. This technique makes it possible to report hierarchical errors in ordinary flat DRC systems.

Polysilicon Gate Depletion Effects in Sub-Micron MOSFETs

It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion effects can safely be ignored. This article aims to quantify poly depletion effects for typical sub-micron device dimensions using ATHENA and ATLAS process and device simulators.