The Berkeley BSIM3SOI model, released in December 1997, is now available within SmartSpice as the MOSFET level=25 model. This model incorporates three separate implementations: the original Berkeley model implementation is invoked with the selector Berk=2; the Silvaco implementation is invoked with Berk=-2.
작성자: Ingrid Schwarz
저자는 아직 경력을 작성하지 않았습니다.
하지만, Ingrid Schwarz 씨는 무려 1784 항목에 기여한 것을 자랑스럽게 생각합니다.
엔트리 Ingrid Schwarz
The paper describes a generalization of the scanline approach  to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d. This problem arises in applications of VLSI layout image processing, e.g., during automated reticle inspection.
This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension of capabilities of flat DRC systems. This technique makes it possible to report hierarchical errors in ordinary flat DRC systems.
One of the most challenging and time consuming tasks
in VLSI design automation is Layout Versus Schematic
(LVS). The problem is to test the consistency between
the actual circuit, represented by the layout, and the
nominal circuit upon which the design was based.
Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?
Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The new modules add to the existing 3D device simulation within ATLAS as shown in Figure 1.
With mounting concern for energy conservation and nature preservation, power electronics is becoming increasingly dominant in everyday life.
It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion effects can safely be ignored. This article aims to quantify poly depletion effects for typical sub-micron device dimensions using ATHENA and ATLAS process and device simulators.
Mesh control in process simulators is one of the major issues tackled by any user. Over the years the meshing algorithms with SSuprem4 and ATHENA have been improved to the stage where most arbitrary structures can be solved. New approaches such as automated ADAPTIVEMESH algorithms or standalone programs such as DevEdit exist to help users.
Q: How can external tools be run inside of Silvaco’s run-time environment DeckBuild? Is it possible to include UNIX commands along with simulator syntax inside an input file?