엔트리 Ingrid Schwarz

New SOI UTMOST Module

7월 1, 1999카테고리: /작성자:

Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater as device geometries shrink. Thus, the search for a suitable replacement has begun, and Silicon-On-Insulator (SOI) technology seems to become the most attractive candidate for a suitable VLSI/CMOS technology.

Hints & Tips May 1999

6월 4, 1999카테고리: /작성자:

A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source/drain junction formation[1] and Reverse Short Channel Effect (RSCE)[2][3]. However for complete simulation of MOS short channel behavior it is necessary to consider the diffusion of the channel implants before the source/drain processing.

Maverick- Hierarchcal Full-Chip Extractor Recent Significant Advances

6월 1, 1999카테고리: /작성자:

Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of Maverick is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.

Circuit Performance Analysis of Multiple ATHENA Transistors Using MixedMode

5월 3, 1999카테고리: /작성자:

In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using ATLAS/MixedMode was introduced. The MOSFETs used in the MixedMode simulation were created using analytical doping profiles specified within ATLAS. This article is intended to investigate some of the effects of process variation on ring oscillator performance. Thus, the individual devices in the ring oscillator circuit are created usingthe two-dimensional process simulation program, ATHENA.

Continous Trap Model for Accurate Device Simulation of Polysilicon TFTs

5월 2, 1999카테고리: /작성자:

There has been a significant increase in the popularity of liquid crystal displays with control circuitry being placed on to the glass (system on a panel). This has been made possible by the technological improvements of thin-film-transistors (TFTs) manufactured on glass substrates. The sudden popularity is a result of the move away from the traditional use of amorphous silicon towards polycrystalline silicon. The increase in performance by this switch has allowed these TFTs to be applied to applications beyond pixel control transistors.

Very Low Energy Boron Implant Simulation Using New BCA Monte-Carlo Model

5월 1, 1999카테고리: /작성자:

ATHENA version 5.0 includes a new Binary Collision Algorithm (BCA) for accurate Monte-Carlo implant modeling down to sub-1keV energies. This new BCA code is a 3D model that takes account of channeling in all possible crystal directions, not just the vertical direction. Accurate modeling of all channeling directions becomes an important factor for low energy implants such as is used by the new generation of very deep submicron devices.

Hints & Tips April 1999

4월 3, 1999카테고리: /작성자:

A. The BSIM3_MG routine in SOI module of UTMOST III can be used to extract SOI model parameters. The SOI BSIM3_MG routine operation is similar to the one in MOS module. However the “Measurement Variables” (Figure 1) and biasing of the SOI device is unique.