A: Modeling of the increase in breakdown voltage at elevated temperatures requires a model to describe the temperature dependence of the impact ionization coefficients. In ATLAS there are two impact ionization models that include lattice temperature dependence. They are the Crowell-Sze model[1] called using the command IMPACT CROWELL and the Selberrherr Model[2] called using the command IMPACT SELB.
The recent advances in PC hardware capability in terms of memory and CPU floating point performance has allowed the possibility of running realistic sized ATHENA and ATLAS problems on PCs. The Fall 1999 release of PC-TCAD will include all the important features of the latest UNIX release. A product chart showing the modules available on PC is in Figure 1.
In order to simulate heterojunction devices accurately, both the thermionic emission and tunneling mechanisms must be considered when calculating transport across hetrojunctions. Drift-diffusion descriptions of carrier mobility are incomplete at abrupt heterointerfaces. New thermionic emission and tunneling models have been incorporated into ATLAS. This paper discusses the models and presents two examples of device simulation.
EXACT is a sophisticated interconnect characterization tool integrated into the DISCOVERY framework. It is designed to build the capacitance coefficient database required by any Layout Parasitic Extraction (LPE) tool. To calculate these coefficients accurately, an internal 3D process simulator creates test structures, such as shown in Figure 1. Then an integrated 3D field solver calculates the capacitance for each device layer and test structure combination. A simple internal script language then reformats the capacitance database so that it can be used with any chip level LPE tool.
The “Binning” routine in UTMOST III MOS module has been greatly enhanced. The bin models can be generated much faster and the routine requires less user interface.
Silvaco now offers the MOS31 JFET/MOSFET model originally developed by Philips [1] as part of the SmartLib product-independent model library. This model is available within SmartSpice as level 31.
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater as device geometries shrink. Thus, the search for a suitable replacement has begun, and Silicon-On-Insulator (SOI) technology seems to become the most attractive candidate for a suitable VLSI/CMOS technology.
A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source/drain junction formation[1] and Reverse Short Channel Effect (RSCE)[2][3]. However for complete simulation of MOS short channel behavior it is necessary to consider the diffusion of the channel implants before the source/drain processing.
Q: I want to draw several long wires, with precise positioning of both ends. I am used to doing this as follows:
Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of Maverick is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.