엔트리 Ingrid Schwarz

The Industry Standard of SOI Technology From Process To Circuit Simulation

11월 1, 1999카테고리: /작성자:

SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design to reduce the effects of the floating-body. FD-SOI device design potentially has the advantage of no floating-body effects but requires very thin silicon films making manufacturing more challenging. As a consequence the optimization of SOI device design requires a coupled solution where both process and circuit simulation can be tied together. Silvaco provides a complete, well integrated simulation software for all aspects of SOI technology. Our SOI specific software includes technology simulation, SPICE model extraction, interconnect parasitic analysis, SPICE circuit simulation and traditional CAD. The TCAD Driven CAD approach provides the most accurate models for both device engineers and circuit designers.

Hints & Tips October 1999

10월 3, 1999카테고리: /작성자:

A. It is likely that there may be some contact problems or defected devices during the data collection. This problem can occur when the log file is open and some good device data has already been stored in the log file. Then it becomes a time consuming process to close the log file, deselect the good devices from the device strategy screen, append the log file and re-measure the device which created the problem.

Scholar: An Enhanced Multi-Platform Schematic Capture

9월 1, 1999카테고리: /작성자:

One of the main features of modern complex CAD systems consists in the ability to support the schematic capture function that provides a user with convenient design entry. In our opinion, a perfect schematic capture subsystem (SC) possesses the following features that differ it from other graphic intensive CAD tools such as layout editors:

Hints & Tips August 1999

8월 4, 1999카테고리: /작성자:

A: Modeling of the increase in breakdown voltage at elevated temperatures requires a model to describe the temperature dependence of the impact ionization coefficients. In ATLAS there are two impact ionization models that include lattice temperature dependence. They are the Crowell-Sze model[1] called using the command IMPACT CROWELL and the Selberrherr Model[2] called using the command IMPACT SELB.

High Performance ATHENA and ATLAS Simulation on PC under NT

8월 3, 1999카테고리: /작성자:

The recent advances in PC hardware capability in terms of memory and CPU floating point performance has allowed the possibility of running realistic sized ATHENA and ATLAS problems on PCs. The Fall 1999 release of PC-TCAD will include all the important features of the latest UNIX release. A product chart showing the modules available on PC is in Figure 1.

New Thermionic Emission and Tunneling Models in ATLAS

8월 2, 1999카테고리: /작성자:

In order to simulate heterojunction devices accurately, both the thermionic emission and tunneling mechanisms must be considered when calculating transport across hetrojunctions. Drift-diffusion descriptions of carrier mobility are incomplete at abrupt heterointerfaces. New thermionic emission and tunneling models have been incorporated into ATLAS. This paper discusses the models and presents two examples of device simulation.

Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using EXACT

8월 1, 1999카테고리: /작성자:

EXACT is a sophisticated interconnect characterization tool integrated into the DISCOVERY framework. It is designed to build the capacitance coefficient database required by any Layout Parasitic Extraction (LPE) tool. To calculate these coefficients accurately, an internal 3D process simulator creates test structures, such as shown in Figure 1. Then an integrated 3D field solver calculates the capacitance for each device layer and test structure combination. A simple internal script language then reformats the capacitance database so that it can be used with any chip level LPE tool.