One of the main features of modern complex Computer-Aided Design Systems is the ability to support the communication between concurrently executing applications within the design process. This feature allows applications, intended for different steps in a design flow, to exchange design data in an integrated manner and therefore to solve design tasks more accurately, easily and quickly.
Q. How can I ensure that the vertical Y.MESH spacing in my process simulation is adequate for my particular implant condition? A. A good technique to check that the mesh is not causing a problem is to perform an integration of the as-implanted species, directly after the implant within ATHENA.
FastBlaze is an ultra-fast physical MESFET and HEMT simulator which incorporates advanced physical models. By designing the simulator and its framework specifically for these devices, Silvaco has optimized device simulation algorithms and data structures for high speed without sacrificing the accuracy of the physical models.
For high temperature, high power applications Silicon Carbide (SiC) continues to be a useful material for device fabrication because of its wide band gap, high breakdown field, and high thermal conductivity [1]. Some common power devices utilizing SiC include the following: Schottky and p-n junction diodes, thyristors, and UMOSFETs. Recent research has further contributed to the characterization of the electrical transport properties of 6H-SiC and 4H-SiC [2].
The Monte Carlo Binary Collision Algorithm (BCA) implant module in ATHENA was introduced in an earlier article [Simulation Standard Vol 10, #5, May 1999] which discussed the accuracy of the simulation model compared to one dimensional measurements using Secondary Ion Mass Spectroscopy (SIMS). In this article we discuss the two dimensional effects that can be simulated using the BCA module that cannot accurately be simulated using analytic models.
A. UTMOST III SOI module has three routines for characterization of the parasitic BJTs of SOI devices. These routines are “IC/VCE”, “Gummel” and “INT_BJT” All routines require to have 5 terminal devices with bulk connection for data collection.
The latest VBIC bipolar model v1.2 of Sep 24 1999 has been integrated into SmartSpice and UTMOST III. It can be invoked by specifying the model selector LEVEL=5 and the version selector VERSION=1.2. in the .MODEL card. This new version becomes the default VBIC model.
A novel extraction method of high frequency small-signal model parameters for MOSFET is proposed. From S-parameter measurement, this technique accurately extracts the MOSFET model parameters including the charge conservation capacitance parameters. To consider charge conservation, nonreciprocal capacitance is considered. The modeled S-parameters fit the measured ones well without any optimization after parameter extraction.
Q: I tried to resize shapes using the DRC command and observed thin “cracks” appeared for polygons with holes (see the left shape in Figure 1). At the same time Expert’s “Resize selected” command does not create such cracks (see the right shape in Figure 1). I do not want DRC resizing command to produce “cracks”. How can I achieve this?
In our previous publication (“Scholar: An Enhanced Multi-Platform Schematic Capture”, Simulation Standard, Vol.10, Number 9, September 1999) we presented the main features of a new-generation schematic capture tool – Silvaco’s Scholar. In this article we are going to describe and analyze the graphical user interface (GUI) of Scholar.