This paper presents research efforts conducted at the IESUPM in the development of an accurate, physically-based solar cell model using the general-purpose ATLAS device simulator by Silvaco. Unlike solar cell models based on a combination of discrete electrical components, this novel model extracts the electrical characteristics of a solar cell based on virtual fabrication of its physical structure, allowing for direct manipulation of materials, dimensions, and dopings. As single junction solar cells simulation was yet achieved, the next step towards advanced simulations of multi-junction cells (MJC) is the simulation of the tunnel diodes, which interconnect the subcells in a monolithic MJC. The first results simulating a Dual-Junction (DJ) GaInP/GaAs solar cells are shown in this paper including a complete Tunnel Junction (TJ) model and the resonant cavity effect occurring in the bottom cell. Simulation and experimental results were compared in order to test the accuracy of the models employed.

A parameterized cell (P-Cell) is a cell with user-specified parameters. It is possible to create customized p-cell instances with different composition according to parameter values. Using P-Cells gives a considerable memory reduction in the case of multiple instancing of a cell.

The latest release of Layout versus Schematic tools from CELEBRITY CAD suite (Maverick full-chip parametric netlist extractor and Guardian hierarchical netlist comparator) delivers a number of significant advances. The engines of both tools were tuned up to achieve essential reduction of running time while processing huge designs.

Q. When I simulate my process flow the simulated profile is always lower than the SRP measurements. What could be causing this? A. In many simulated process flows the surface oxide is etched completely off after which there may be some diffusion cycles.

This article will present an efficient and original methodology for global and predictive modeling of low energy Boron, BF2 and Arsenic ion implantation, in the suitable range for sub-100nm CMOS technology.