엔트리 Ingrid Schwarz

Evaluating of the Breakdown Voltage of the Super-Junctions Using ATLAS

High Voltage Power Devices using super junction or multi RESURF effect have a relatively high BV with a drastic reduction in the on-state resistance (Ron)[1-2]. Several Techniques such as buried multi-epitaxial growth[3], Super Trench Power MOSFET process[4], Vapor Phase Doping[5] and trench filling epitaxial Si growth[6], have been applied to formation of the high aspect ratio p/n column structures. In blocking mode, the adjacent N- and P- regions deplete into each other laterally. For this junction, the process simulation was considered with several implant ionization process steps[3]. The condition of exact charge balance is important in obtaining the stable high Breakdown Voltage (BV).

Active and Isolation Trench Fabrication for 100V Vertical LOCOS Power MOSFETS with VICTORY PROCESS and ATHENA

Vertical LOCOS (VLOCOS) power MOSFET structures are becoming increasingly popular [1-3] for 100 V rated applications due to their high packing density, superior temperature characteristics and low on-state resistance. It has been shown that through careful design, the on-state resistance can exceed the silicon limit [4].

Hints, Tips and Solutions – Visualizing Drift and Diffusion Current Densities

One of the most important features of TCAD simulation is that the TCAD tools encapsulate the physics of the processes or devices being studied. For the user, this can develop and reinforce an intuitive understanding. In device physics, it can be very helpful to be able to look at the different components of current density. Sze1 presented a nice example of the difference between drift and diffusion currents, based on the Haynes-Schockley experiment2. This note shows simulation results of the Haynes-Schockley experiment using ATLAS with Luminous.

Simulating SiGe and Impurity Dependent Stress

The simulation of stress during device fabrication is becoming increasingly important and is often now deliberately introduced during fabrication to enhance device performance. The induced stress can take the form of deposited amorphous materials, such as silicon nitride or can be induced epitaxially by the growth of silicon germanium (SiGe) for example.

Physical 3D Single Event Upset Simulation of a SRAM Cell with VICTORY DEVICE and SmartSpice

VICTORY DEVICE simulation framework includes tools for 1D, 2D and 3D simulation of modern semiconductor technologies. VICTORY DEVICE implements a full tetrahedral meshing engine for fast and accurate simulation of complex 3D geometries. Built in and user defined mesh refinement criteria can be used for customization of the mesh during a simulation. This is the case for Single Event Upset (SEU) simulation. The simulation of SEU phenomena in 3D structures is highly complicated due to the presence of large gradients in physical quantities near the SEU track. In order to perform accurate and stable simulations of SEU strikes in 3D structures, it is essential to have fairly dense mesh near the center of the SEU track while maintaining a coarser mesh far from the track for efficiency. The aim of this paper is to illustrate how a SRAM cell subject to SEU can be accurately simulated.

Electrically Controlled Silicon-based Photonic Crystal Chromatic Dispersion Compensator with Ultra Low Power Consumption

We show full 3-Dimensional (3D) electrical and optical simulation of a tunable silicon-based Photonic Crystal (PhC) Chromatic Dispersion Compensator (CDC) with high power efficiency and ultra-low power consumption (114nW), operating at a speed of 40.5MHz. The device exploits a structure where the optical field maximum is not in a PhC waveguide, but rather in a hybrid Si3N4/Si/SiO2 structure that will allow greater ease of fiber coupling due to larger mode size and reduced loss. The CDC is broadband, and produces constant 2nd order chromatic dispersion over an optical communication band such as C-band.

SONOS/SANOS Simulation in ATLAS

Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) Non-Volatile memory structures can be simulated using ATLAS. The basic principle of these devices is the use of a charge trapping Silicon Nitride layer embedded in the oxide layer separating the gate from the channel. This results in an oxide layer between the gate and the Silicon Nitride layer, and another between the Nitride layer and the semiconducting channel (Figure 1). The Silicon Nitride layer can be charged by quantum mechanical tunneling or by hot carrier injection. This results in a shift in the turn-on voltage of the NVM device. The trapped charge can be discharged by quantum mechanical tunneling or by injecting hot carriers of the opposite polarity, thereby erasing the threshold Voltage shift.[1] [2]