The silicon germanium heterojunction bipolar transistor (SiGe HBT) is a promising technology for combining the operating speed of compound material devices with the production capability of bulk silicon. The presence of a narrower-bandgap material in the base region where most of the bandgap offset occurs in the valence band, creates an energy well for holes. With the lower energy barrier, a lower hole current density can be obtained for a given electron current density increasing the transistor’s gain [1]. Thus the base can then be highly doped, greatly increasing high frequency performance whilst still retaining a reasonable gain. For this reason, the diffusion of boron in SiGe is of great interest.

Impact ionization plays an important role in the design of many semiconductor devices. Since impact ionization is both temperature and electric field dependent, it is important to use a model which has the correct functional behavior. For most devices impact ionization defines the safe region of operation within a moderate range of temperatures, so the temperature dependence of impact ionization is of lessor importance than the field dependence. However, for devices which must operate outside of the usual temperature limits, or which carry enough current to heat themselves out of those limits, both field dependence and temperature dependence of the model must be accurate.

BSIM3SOI version 3.0 model was released on May 2002 by UC Berkeley. This model includes both Partially and Fully depleted models. This model is now implemented in SmartSpice and can be selected according to LEVEL selector.

HiSIM is a MOSFET model for SPICE circuit simulation that has been developed by Hiroshima University and STARC Company. This model present several advantage on the extraction point of view, with a reasonable number of parameters, a physical reliability of the equations for a wide range of geometries (down to 0.1um) and a unified description of devices characteristics for all bias conditions. It has been implemented in Silvaco Spice Simulator, SmartSpice and in our current extraction software UTMOST III.

A new version of Savage DRC system taps the full power of multiprocessor computers by introducing simultaneous execution of DRC commands from a DRC deck. A DRC deck is a set of DRC rules to be performed for a given layout. For typical DRC decks, the described approach alone delivers high processor utilization and speed-up. Further improvements are possible using parallelization by decomposition of IC layout data and exploiting its hierarchy.