Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice interface for it. This new interface software allows users to replace Spectre with SmartSpice as the analog simulation engine without disrupting the design flow.
A new notation has been introduced into SmartSpice to allow a compact expression of a multiple bit wire buss to be used. From this expression the user can simply state the members of a wire bus he wants to generate vectors for or probe. This syntax can be used in conjunction with .SAVE .PROBE
Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate of accurate netlist extraction. This simulation standard will detail this important area of netlist extraction and will provide an insight into Silvaco International’s netlist extraction tools to aid the circuit design engineer.
HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance extraction tool.
SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco’s Maverick, which is a part of Guardian LVS/ERC. While being fully compliant with Maverick, HIPEX-NET has many advantages over Maverick. The comparison chart in Table 1 shows the critical features, which make HIPEX-NET much more powerful for layout verification than Maverick.
In previous versions of Guardian DRC there were only two ways of measuring the distance between two segments: the ordinary, Euclidean metric, and the square metric, which behaves differently when measuring distances from a corner of a shape. With decreasing feature sizes Euclidean metric does not always provide the adequate measurement of tolerances required during the IC fabrication. Therefore various DRC systems introduced other types of measurement. This article describes how Guardian DRC system performs measurements required for the execution of DRC spacing checks, which are based on separations between line segments (“width”, “indistance”, “outdistance”, “ovdistance”, “distance”, “compdistance”).
Q: I would like to highlight two nodes at the same time in Expert. I currently use Verification->Node Probing->Pick Node to highlight a node, but I donít see how I can have 2 nets highlighted at the same time.
Spreading Resistance Profiling (SRP) retains its popularity in the semiconductor industry by an inexpensive means of capturing dopant profile information. However, device engineers often incorporate SRP data into process simulation studies without properly considering SRP’s many limitations. Failing to account for these limitations jeopardizes the reliability of the data and potentially lead designers to incorrect conclusions about a device.
An eye diagram is a convenient way to visualise how the waveforms used to send multiple bits of data can potentially lead to errors in the interpretation of those bits. This is the so-called problem of intersymbol interference. An eye diagram is also a useful means for readily obtaining information regarding the timing jitter, voltage swing and transition time of the modulation data. The eye diagram operation in ATLAS is a post processing function where the eye diagram is created by taking the time domain signal and overlapping the traces for a certain number of symbols. The time domain signal in this article represents the output from a directly modulated semiconductor laser. The modulation of the laser drive current takes a pseudo-random form.
An effective device structure for reducing leakage current in BH laser diodes with semiin-sulation doped Fe in InP blocking layers has been analyzed [3]. In this study, the leakage current and light output power as a function of the leakage current path is examined. The blocking region used follows p-n-p-n structure.