엔트리 Graham Bell
Victory TCAD Suite: How to use it for fast, efficient, and accurate simulation of power semiconductor devices
Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. The introduction of Victory Process, Victory Mesh, and Victory Device significantly increases the functionality and flexibility of the tool set available to designers. In this article we look at how some of the features of this suite of tools improve the efficiency of the design flow.
TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate
The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna switches which are compatible with multimode GSM/EDGE, TD/WCDMA, and LTE systems exhibit higher integration levels and have become the fastest growing mobile phone submarket. CMOS-SOI processes, especially with thin silicon, have the potential to rival the FoM that was traditionally feasible only with GaAs technologies.
Hints and Tips: Specify Units in the Victory Process Material Statement
It is crucial for any kind of calculations that units are consistent between equations and modeling modules. Often different units are used in various experimental and theoretical fields. Therefore, we have introduced standardized unit conversions, making it possible to specify any desired units when changing parameters within the MATERIAL statement.
Hints and Tips: How do I Load, Remesh, and Refine an Existing Device Structure in Victory Mesh?
Victory Mesh initially supported loading and remeshing of the saved status from Victory Process. Victory Mesh 1.5.0 onwards is now able to load and remesh individual structure files (.str files), including associated scalar fields. These include the result of a device simulation from software such as Victory Device and Atlas.
Weebit Nano와 실바코가 ReRAM 도입을 증가시킬 새로운 시뮬레이션 기능을 개발
2020년 2월 19일
에너지 효율적인 신경 컴퓨팅을 위한 2D 진동 신경 네트워크
2020년 2월 5일
실바코 TCAD 소개 및 기본 – 3부
2019년 5월 29일 | 3:00am-3:30am (한국 시각)
Victory Process와 함께 TCAD 공정 시뮬레이션에 대해 논의합니다. 반도체 공정 시뮬레이션, 구조 설계 및 공정 에뮬레이션 등의 기본 사항에 대해 살펴봅니다.
IBIS Models in SmartSpice
The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines…) on printed circuit boards (PCBs).
New Features in SmartSpice 2.3.4.C
A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the suspended state. This allows generated data checks during the simulation run and therefore ensuring relevant simulation data is generated. This feature allows a user to check intermediate simulation results and/or save (if necessary) on the fly.