The Atlas syntax is flexible enough to allow the definition of sinusoidal nodal voltages by defining them on the SOLVE statement line. To illustrate this the structure shown in Figure 1 has been used. Before the sinusoidal pulse is applied a dc operating condition is set with
This article presents a high frequency SPICE model parameter extraction method for CMOS devices. Current compact MOS models are developed for low frequency applications and provide good fits for DC, conductances and intrinsic capacitances. However for the gigahertz frequency range external components have to be modeled and added to the compact model as macro model elements. The macro model presented in this article provides good results up to 10 GHz.
New improvements have been added to Shur a-Si:H and Poly-Si Thin Film Transistors models. These enhancements include self-heating effect and a new charge conservation model.
This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.Application
This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.
For the UTMOST III versions greater than 17.2.0.R, the UTMOST users can measure the CJSWG (CJGATE) capacitance using the “CJ/CJSW” routine. The CJ/CJSW routine in MOS technology has been modified to measure the CJSWG (Peripheral portion of the junction capacitance under the gate) capacitance.
Cross-Sectional Viewer is a tool within Expert to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout. Cross-sectional Viewer is a link between the layout and the resulting device. It allows the designer to examine cross-sections of the device being designed. Cross-sectional drawings are useful for understanding design rules, parasitic coupling and other design and fabrication problems.
The functionality of several features of Expert layout editor has been enhanced to deal with hierarchical layouts in more convenient ways.
An important step in electronic circuit design is layout versus schematic verification (LVS)
Q: Often I need to measure big objects. It order to position the ruler precisely I must zoom in at one end, zoom out that zoom again in at the other end. Is it possible too make this operation more convenient? For example, can I start the measurement in one window and finish it in another one?
In previous Simulation Standard articles (Nov 97 & Nov 98) FastBlaze has been presented as a new, highly efficient approach to simulating advanced HEMTs and MESFETs. Conventional device simulators often suffer from slow execution times, leading to a trade off between mesh density and physical model complexity against CPU run time and convergence. This requires engineers to compromise accuracy to achieve a reasonable throughput.