HiSIM-1.2 parameter extraction methodology was discussed in detail in a previous issue of Silvaco Simulation Standard [1]. This article is meant to provide the precise UTMOST-III local optimization strategies to UTMOST-III users who are interested in HiSIM-1.2 parameter extraction. The developed strategies were applied to the actual 90 nm technology devices [2]. The HiSIM-1.2 proved the capability to give the scalable model down to 100 nm from 10 um channel length with no parameter binning.

Customers are starting to use 64bit machines with large hard drives and Gigs of RAM and tend to forget the limitations imposed by a 32bit operating system. If you have more than 2Gigs of RAM in a system the extra is not used by the 32bit compiled program as it is not possible to address a contigeous memory space bigger than this when you have 1 parity bit and 31 data bits (2^31). If you are however using our 64bit compiled version of SmartSpice then you can use as much memory (RAM) as you care to put into the system (2^63 is a huge number compared to the 32 bit case).

Overview

To extract parasitic capacitances from a circuit layout, you need to perform the following steps:

Q. Every time I create a new project or library, an empty cell with the same name is created in my project. What do I need to setup to avoid the creation of this empty cell?

On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower. The quantitative consideration of coupling capacitance based on three-dimensional calculation is indispensable. Conventional advanced LSI design tools and methodology are limited in their ability to optimize the LPE library. As a result, the discussion of LPE tool accuracy and extracted parasitic results lack significant quantitative generality.