{"id":66237,"date":"2026-07-29T10:44:13","date_gmt":"2026-07-29T17:44:13","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/accelerating-manufacturing-aware-simulations-for-photonic-integrated-circuits-with-ftco-and-digital-twins-2\/"},"modified":"2026-07-29T11:00:56","modified_gmt":"2026-07-29T18:00:56","slug":"accelerating-manufacturing-aware-simulations-for-photonic-integrated-circuits-with-ftco-and-digital-twins-2","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/accelerating-manufacturing-aware-simulations-for-photonic-integrated-circuits-with-ftco-and-digital-twins-2\/","title":{"rendered":"Accelerating Manufacturing-Aware Simulations for Photonic Integrated Circuits with FTCO\u2122 and Digital Twins"},"content":{"rendered":"
\n

Accelerating Manufacturing-Aware Simulations for Photonic Integrated Circuits with FTCO\u2122 and Digital Twins<\/b><\/h1>\n

Abstract<\/strong><\/p>\n

\"\"Photonic integrated circuit (PIC) performance is increasingl<\/span>y bounded by fabrication realities such as sidewall angle, critical-dimension bias, thickness variation, and line-edge roughness, which idealized, as-drawn FDTD simulations fail to capture. Here, we show a Fab Technology Co-Optimization (FTCO) workflow that con<\/span>nects GDS layout import, three-dimensional process simulation, GPU-accelerated FDTD, design of experiments (DOE), with AI-based surrogate modeling. We show that when manufacturing variations are included in the modeling that the simulation results align well with experimentally reported results. A directional-coup<\/span>ler DOE with 25 unique combinations of 4 different process variations requiring a 65-million-cell 3D FDTD model and completes in under 10 hours on a single NVIDIA A100-equipped workstation is showcased. The generated digital twin provides intuitive and real-time access to the process-to-performance relationship for non-simulation experts: A game-changer in the industry.<\/p>\n<\/div><\/section><\/div>

<\/div>