{"id":29879,"date":"2020-02-26T17:52:49","date_gmt":"2020-02-26T17:52:49","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/tft-technology\/"},"modified":"2021-12-13T13:50:52","modified_gmt":"2021-12-13T21:50:52","slug":"tft-technology","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/published-papers\/tft-technology\/","title":{"rendered":"TFT Technology"},"content":{"rendered":"
\n

TFT Technology<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

Yu-Shien Shiah1,<\/sup>\u00a0Kihyung Sim1<\/sup>, Yuhao Shi1<\/sup>, Katsumi Abe2<\/sup>, Shigenori Ueda3<\/sup>, Masato Sasase1<\/sup>, Junghwan Kim1<\/sup>\u00a0& Hideo Hosono1,3<\/sup><\/div>\n
Mobility\u2013stability trade-off in oxide thin-film transistors<\/a><\/div>\n
    \n
  1. Materials Research Center for Element Strategy, Tokyo Institute of Technology, Yokohama, Japan<\/li>\n
  2. Silvaco Japan, Japan<\/li>\n
  3. WPI-MANA, National Institute for Materials Science, Ibaraki, Japan<\/li>\n<\/ol>\n
    Nature Electronics volume 4, pages800\u2013807 (2021)<\/div>\n

    Hyeon-Jun Lee1<\/sup>\u00a0, Katsumi Abe\u00a02<\/sup>
    \n    A Study on the Effect of Pulse Rising and Falling Time on Amorphous Oxide Semiconductor Transistors in Driver Circuits<\/a><\/p>\n

      \n
    1. Institute of Convergence, Daegu Gyeonbuk Institute of Science and Technology (DGIST), Daegu, South Korea<\/li>\n
    2. Silvaco Japan Company, Ltd., Kyoto, Japan<\/li>\n<\/ol>\n

      IEEE Electron Device Letters, Volume: 41 Issue: 6<\/p>\n

      Hwarim Im1<\/sup>, Hyunsoo Song1<\/sup>, Jaewook Jeong2<\/sup>, Yewon Hong1<\/sup>, Yongtaek Hong1<\/sup>,
      \n“Effects of the defect creation on the bidirectional shift of threshold voltage with hump characteristics of InGaZnO TFTs Under Bias and Thermal Stress”<\/p>\n

        \n
      1. Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
        \nInter-University Semiconductor Research Center, Seoul Nat. Univ., Seoul, South Korea<\/li>\n
      2. Division of Nano and Bio Technology, Daegu Gyeongbuk Institute of Science and Technology,
        \nDaegu, South Korea<\/li>\n<\/ol>\n

        Active-Matrix Flatpanel Displays and Devices (AM-FPD) 2014, pp.153-156<\/p>\n

        Copyright 2014 The Japan Society of Applied Physics<\/span><\/p>\n

        Kimura M., Bundo K., Imuro Y., Sagawa Y., Setsu K.,
        \n“Chronoamperometry Using Integrated Potentiostat Consisting of Poly-Si Thin-Film Transistors”
        \nElectron Device Letters, IEEE, Vol. 32, Issue 2, Feb 2011, pp. 212&214<\/p>\n

        Kasakawa T., Tabata H., Onodera R., Kojima H., Kimura M., Hara H., Inoue S.,
        \n“An Artificial Neural Network at Device Level Using Simplified Architecture and Thin-Film Transistors”
        \nIEEE Transactions on Electron Devices, Vol. 57, Issue 10, October 2010, pp. 2744&2750<\/p>\n

        Aapo Varpula,
        \n“Modeling of transient electrical characteristics for granular semiconductors”,
        \nJournal of Applied Physics, Vol. 108, Issue: 3, 2010, pp. 034511&034511-13.<\/p>\n

        Mutsumi Kimura,
        \n“Extraction of trap densities in poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on temperature and time of post annealing”,
        \nSolid-State Electronics, Vol. 54, Issue 12, December 2010, pp. 1500-1504.<\/p>\n

        Meng Zhang, Mingxiang Wang,
        \n“An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors”,
        \nMicroelectronics Reliability, Vol. 50, Issue 5, May 2010, pp. 713-716.<\/p>\n

        Gupta Dipti, Katiyar M., Gupta Deepak,
        \n“An analysis of the difference in behavior of top and bottom contact organic thin film transistors using device simulation”,
        \nOrganic Electronics, Vol. 10, Issue 5, August 2009, pp. 775-784<\/p>\n

        M. G. Ancona, A. Svizhenko,
        \n“Physics of tunneling from a macroscopic perspective”,
        \n2008 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2008), pp. 361-4, 2008.<\/p>\n

        A. Jamshidi-Roudbari, P. C. Kuo, M. K. Hatalis,
        \n“High voltage, moderate current thin film transistor for actuator applications”,
        \nECS Transactions&Sensor, Actuators, and Microsystems General Session, Vol. 11, Issue 14, 2008, pp. 31-39<\/p>\n

        Hsiao-Wen Zan, Kuang-Ming Wang,
        \n“The Channel Length Extension in Poly-Si TFTs With LDD Structure”,
        \nElectron Device Letters, IEEE Vol. 29, Issue 9, Sept. 2008 pp. 1034&1036.<\/p>\n

        Kathy Boucart, Adrian Mihai Ionescu,
        \n“A new definition of threshold voltage in Tunnel FETs”,
        \nSolid-State Electronics, Vol. 52, Issue 9, September 2008, pp. 1318-1323<\/p>\n

        Amit Sehgal, Tina Mangla, Mridula Gupta and R.S. Gupta,
        \n“Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency”,
        \nThin Solid Films, Vol. 516, Issue 8, 29 February 2008, pp. 2162-2170<\/p>\n

        Domenico Palumbo, Silvia Masala, Paolo Tassini, Alfredo Rubino, and Dario della Sala
        \n“Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors”,
        \nIEEE Transactions on Electron Devices, VOL 54, NO 3, March 2007.<\/p>\n

        Kiyoshi Harada, Takuto Yoshino, Tohuru Yasuhara, Mutsumi Kimura, Daisuke Abe, Satoshi Inque, and Tatsuya Shimoda,
        \n“Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation”
        \nJapanese Journal of Applied Physics, Vol. 46, No 3B, 2007 pp. 1308-1311<\/p>\n

        Domenico Palumbo, Silvia Masala, Paolo Tassini, Alfredo Rubino, Dario della Sala,
        \n“Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors”
        \nElectron Devices, IEEE Transactions on Vol. 54, Issue 3, March 2007 pp. 476-482<\/p>\n

        Ilias Pappas, Stilianos Siskos, Charalabos A. Dimitriadis,
        \n“A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays”
        \nElectron Devices, IEEE Transactions on Vol. 54, Issue 2, Feb. 2007 pp. 219-224<\/p>\n

        M. Kimura, T. Yasuhara, K. Harada, D. Abe, S. Inoue, T. Shimoda,
        \n“Device simulation of polycrystalline-silicon thin-film transistors with trap states at front and back oxide interfaces”
        \nKyokai Joho Imeji Zasshi\/Journal of the Institute of Image Information and Television Engineers<\/p>\n

        M. J. Kumar, S. D. Roy,
        \n“A new high breakdown voltage lateral Schottky collector bipolar transistor on SOI: Design and analysis”
        \nIEEE Transactions on Electron Devices, Vol. 52, Issue 11, November 2005, pp. 2496-2501<\/p>\n

        A. Sehgal, T. Mangla, S. Chopra, M. Gupta, R. S. Gupta,
        \n“Sub-threshold analysis and drain current modeling of polysilicon thin-film transistor using Green\u00b4s function approach”
        \nIEEE Transactions on Microwave Theory and Techniques, Vol. 53, Issue 9, pp. 2682-2687<\/p>\n

        Bawedin M., Cristoloveanu, S., Yun, J.G., Flandre, D.,
        \n“A new memory effect (MSD) in fully depleted SOI MOSFETs”
        \nSolid-State Electronics, Vol. 49, Issue 9 SPEC. ISS., September 2005, pp. 1547-1555<\/p>\n

        F. Balon, J. M. Shannon,
        \n“Modeling of source-gated transistors in amorphous silicon”
        \nJournal of the Electrochemical Society, Vol. 152, Issue 8, 2005.<\/p>\n

        L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson, C. Gerardi,
        \n“Electrostatic effect of localised charge in dual bit memory cells with discrete traps”
        \nESSCIRC 2004&Proceedings of the 34th European Solid-State Device Research Conference, ESSCIRC 2004, pp. 249-252<\/p>\n

        Y. D. Hong, Y. T. Yeow, W. -K. Chim, K. -M Wong, J. J. Kopanski,
        \n“Influence of interface traps and surface mobility degradation on scanning capacitance microscopy measurement”
        \nIEEE Transactions on Electron Devices, Vol. 51, Issue 9, September 2004, pp. 1496-1503.<\/p>\n

        S. Sedlmaier, K. K. Bhuwalka, A. Ludsteck, M. Schmidt, J. Schulze, W. Hansch, I. Eisele,
        \n“Gate-controlled resonant interband tunneling in silicon”
        \nApplied Physics Letters, Vol. 85, Issue 10, 6 September 2004, pp. 1707-1709.<\/p>\n

        H. Tango, M. Suganuma, G. Usami, Y. Nogami,
        \n“Hot-carrier instability in N-And P-channel poly-Si TFTs”
        \nProceedings&Electrochemical Society, Vol. PV 2004-15, pp. 104-111<\/p>\n

        Mutsumi Kimura, Daisuke Abe, Satoshi Inoue and Tatsuya Shimoda,
        \n“Extraction of Trap Densities at Front- and Back-Interfaces in poly-Si TFTs with Plasma Treatment and Vapor Heat Treatment”
        \nExt. Abstr. (51th Spring Meet. 2004); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Mutsumi Kimura, Chiharu Iriguchi, Satoshi Inoue and Tatsuya Shimoda,
        \n“Device Simulation of Fine TFTs”
        \nExt. Abstr. (51th Spring Meet. 2004); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Temperature Dependence of Electric Conductance in Poly-Si Thin Films and Determination of the Effective Richardson Constant”
        \nExt. Abstr. (51th Spring Meet. 2004); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Hiroyuki Ikeda,
        \n“Characterization of Switching Transient Behaviors in Polycrystalline-Silicon Thin-Film Tansistors”
        \nJpn. J. Appl. Phys. Vol.43. Issue 2, 2004, pp. 477-484<\/p>\n

        Mutsumi Kimura, Simon W.-B. Tam, Satoshi Inoue and Tatsuya Shimoda,
        \n“Extraction of Trap Densities at Front- and Back-Interfaces in Thin-Film Transistors”
        \nJpn. J. Appl. Phys. Pt. 1, Vol. 43, Issue 1, Jan. 2004, pp. 71-76<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Dependence of Transistor Characteristics on Trap Densities at the Front- and Back-Oxide Interfaces in Thin-Film Transistors”
        \nProc. IDW \u00b403, pp. 331-334, Dec. 2003<\/p>\n

        F. M. Hossain, J. Nishii, S. Takagi, A. Ohtomo, T. Fukumura, H. Fujioka, H. Ohno, H. Koinuma, M. Kawasaki,
        \n“Modeling and simulation of polycrystalline ZnO thin-film transistors”
        \nJournal of Applied Physics, Vol. 94, Issue 12, 15 December 2003, pp. 7768-7777<\/p>\n

        M. Kimura, T. Takizawa, M. Miyasaka, S. Inoue, T. Shimoda,
        \n“Analytical Current-Voltage Model for Polycrystalline Silicon Thin-Film Transistors”
        \nDiffusion and Defect Data Pt.B: Solid State Phenomena, Vol. 93, 2003, pp. 79-84<\/p>\n

        Mutsumi Kimura, Daisuke Abe, Simon W.-B. Tam, Satoshi Inoue and Tatsuya Shimoda,
        \n“Analysis of Plasma Treatment and Vapor Heat Treatment for Thin-Film Transistors by Extracting Trap Densities at Front- and Back-Interfaces”
        \nProc. IDW \u00b403, pp. 1669-1670, Dec. 2003<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Dependence of Poly-Si TFT Characteristic on Oxide Interface Traps and Grain Boundary Traps and its Application to Diagnosis of Fabrication Processes”
        \nTechnical Report of IEICE, SDM2003-180, pp. 7-12, Dec. 2003 [in Japanese]<\/p>\n

        D. Dosev, B. Iniguez, L. F. Marsal, J. Pallares, T. Ytterdal,
        \n“Device simulations of nanocrystalline silicon Thin film transistors”
        \nSolid-State Electronics, Vol. 47, Issue 11, November 2003, pp. 1917-1920<\/p>\n

        Mutsumi Kimura,
        \n“Electrical Characteristic Analysis and Device Simulation of Polycrystalline Silicon Thin-Film Transistors”
        \nTechnical Report of IEICE, SDM2003-161, pp. 1-8, Oct. 2003 [in Japanese]<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Extraction of Trap Densities at Front- and Back-Interfaces in Poly-Si TFTs”
        \nExt. Abstr. (64th Autumn Meet. 2003); Japan Society of Applied Physics, No. 2, pp. 776, Sep. 2003<\/p>\n

        Mutsumi Kimura,
        \n“Characteristic Diagnosis of Thin-Film Transistor using Device Simulation”
        \nExt. Abstr. (64th Autumn Meet. 2003); Japan Society of Applied Physics, No. 2, pp. 777, Sep. 2003<\/p>\n

        Satoshi Inoue, Mutsumi Kimura and Tatsuya Shimoda,
        \n“Analysis and Classification of Degradation Phenomena in Polycrystalline-Silicon”
        \nJpn. J. Appl. Phys. Vol. 42 (2003) pp. 1168-1172<\/p>\n

        Y. Uraoka, N. Hirai*, H. Yano, T. Hatayama and T. Fuyuki,
        \n“Analysis of Reliability in Low-Temperature Polt-Si Thin Film Transistors using Pico-second Time-Resolved Emission Microscope”
        \nIEDM 2002, Dec 2002. pp. 577-580<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Dependence of TFT Characteristics on Trap Densities at the Front- and Back-Oxide Interfaces”
        \nExt. Abstr. (63th Autumn Meet. 2002); Japan Society of Applied Physics, No. 2, pp. 785, Sep. 2002<\/p>\n

        Mutsumi Kimura, Teruo Takizawa, Mitsutoshi Miyasaka, Satoshi Inoue and Tatsuya Shimoda,
        \n“Analytical I-V Model for Poly-Si TFTs”
        \nPOLYSE 2002, pp. 73, Sep. 2002<\/p>\n

        Mutsumi Kimura, Ryoichi Nozawa, Satoshi Inoue, Tatsuya Shimoda, Basil O.-K. Lui, Simon W.-B. Tam and Piero Migliorato,
        \n“Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors”
        \nTrans. IEICE Vol. J85-C, No. 8, pp. 673-683, Aug. 2002 [in Japanese]<\/p>\n

        Y. D. Son, K. S. Cho, S. Y. Yoo, J. U. Kwak, K. H. Kim and JinJang,
        \n“A p-channel SMC poly-Si thin film-transistor with a GOLDD structure”
        \nCurrent Applied Physics, Vol. 2, Issue 4, August 2002, pp. 269-272<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Dependence of Poly-Si TFT Characteristics on Oxide Inteerface Traps and Grain Boundary Traps”
        \nDig. AM-LCD \u00b402, pp. 255-258, Jul. 2002<\/p>\n

        Mutsumi Kimura,
        \n“Characterization and Simulation of Thin-Film Transistors”
        \nAWAD 2002, pp. 169-174, Jul. 2002<\/p>\n

        Hiroyuki Ikeda,
        \n“Evaluation of grain boundary trap states in polycrystalline-silicon thin-film transistors by mobility and capacitance measurements”
        \nJournal of Applied Physics Vol. 91, No.7 April 2002, pp. 4637-4645<\/p>\n

        Mutsumi Kimura, Teruo Takizawa, Satoshi Inoue and Tatsuya Shimoda,
        \n“Analytical Current-Voltage Model for Thin-Film Transistors”
        \nJ. Appl. Phys. Vol. 80, No. 13, pp. 2326-2328, April 2002<\/p>\n

        N. Tosic Golo, F. G. Kuper and T. Mouthaan,
        \n“Zapping thin film transistors”
        \nMicroelectronics Reliability, Vol. 42, Issues 4-5, April-May 2002, pp. 747-765<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Extraction of Defect Density at the Oxide-Si Interface and Grain Boundary for Poly-Si TFTs and SOI FET”
        \nExt. Abstr. (49th Spring Meet. 2002); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Y. Nanno, K. Senda, H. Tsutsu, H. Uchiike,
        \n“Development of a new design simulator for poly-Si TFTs to optimize the lightly doped drain structure”
        \nJournal of the Society for Information Display, Vol. 10, Issue 1, 2002, pp. 101-106<\/p>\n

        Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda, Simon W.-B. Tam, Basil O.-K. Lui, Piero Migliorato and Ryoichi Nozawa,
        \n“Extraction of Trap States in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors and Analysis of Degradation by Self-Heating”
        \nJ. Appl. Phys. Vol. 91, No. 6, pp. 3855-3858, March 2002<\/p>\n

        M. Kimura,
        \n“Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin-film transistors”
        \nElectronics and Communications in Japan, Part II: Vol. 88, Issue 2, pp. 1\u201310, February 2005<\/p>\n

        Y. Furuta, H. Mizuta, K. Nakazato and et al.,
        \n“Carrier transport across a few grain boundaries in highly doped polycrystalline silicon”
        \nJpn. J. Appl. Phys. 2, Vol. 40, Jun. 2001, pp. L615&L617.<\/p>\n

        Mutsumi Kimura, O. K. Basil Lui, William French, Itaru Kamohara, Satoshi Inoue, Tatsuya Shimoda and Piero Migliorato,
        \n“Development of Poly-Si TFT Models for Device Simulation: In-Plane Trap Model and Thermionic Emission Model”
        \nProc. Asia Display \/ IDW \u00b401, pp. 423-426, Oct. 2001<\/p>\n

        M. Estrada, A. Cerdeira, A. Leyva, M. N. P. Carreno and I. Pereyra,
        \n“Optimization of the\u00a0i-<\/i>layer width of Cr-a-Si:H\u00a0PIN<\/i>\u00a0X-ray detectors”
        \nThin Solid Films, Vol. 396, Issues 1-2, 21 September 2001, pp. 237-241<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Device Simulation of Thermionic Emission at Grain Boundaries in Doped Poly-Si Films”
        \nExt. Abstr. (62th Autumn Meet. 2001); Japan Society of Applied Physics, No. 2, pp. 682, Sep. 2001<\/p>\n

        Mutsumi Kimura, Simon W.-B. Tam, O. K. Basil Lui, Ryoichi Nozawa, Satoshi Inoue, Tatsuya Shimoda and Piero Migliorato,
        \n“Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors”
        \nDig. AM-LCD \u00b401, pp. 191-192, Jul. 2001<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Development of Device, Circuit and Liquid-Crystal Simulators for Polycrystalline Silicon Thin-Film Transistors and Their Applications”
        \nDissertation, Tokyo Univirsity of Agriculture and Technology, Jun. 2001<\/p>\n

        Magali Estrada, Antonio Cerdeira, Adelmo Ortiz-Conde and Francisco Garcia,
        \n“Determination of trap cross-section in a-Si:H pi-n diodes parameters using simulation and parameter extraction”
        \nMicroelectronics Reliability, Vol. 41, Issue 4, April 2001, pp. 605-610<\/p>\n

        M. Baudet, H. Lhermite, T. Mohammed-Brahim,
        \n“Simulation of the backward current in polycrystalline silicon thin-film transistors”
        \nDiffusion and Defect Data Pt.B: Solid State Phenomena, Vol. 80-81, 2001, pp. 379-384<\/p>\n

        Mutsumi Kimura, Ryoichi Nozawa, Satoshi Inoue and Tatsuya Shimoda,
        \n“Current Density Enhancement at Active Layer Edges in Polycrystalline Silicon Thin-Film Transistors”
        \nJpn. J. Appl. Phys. Vol. 40 (2001) pp.L26-L28<\/p>\n

        Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda and Toshiyuki Sameshima,
        \n“Current Paths over Grain Boundaries in Polycrystalline Silicon Films”
        \nJpn. J. Appl. Phys. Vol. 40 (2001) pp. L97-L99<\/p>\n

        Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda and Toshiyuki Sameshima,
        \n“Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density”
        \nJpn. J. Appl. Phys. Vol. 40 (2001) pp. 49-53<\/p>\n

        Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda and Toshiyuki Sameshima,
        \n“Device Simulation of Carrier Transport through Grain Boundaries in Lightly Doped Polysilicon Films and Dependence on Dopant Density”
        \nJpn. J. Appl. Phys. Vol. 40 (2001) pp. 5237-5243<\/p>\n

        Mutsumi Kimura, Ryoichi Nozawa, Satoshi Inoue and Tatsuya Shimoda,
        \n“Extraction of Defect Density at the Oxide-Si Interface and Grain Boundary in Poly-Si TFTs”
        \nExt. Abstr. (48th Spring Meet. 2001); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Mutsumi Kimura, Ryoichi Nozawa, Satoshi Inoue, Tatsuya Shimoda, Basil O.-K. Lui, Simon W.-B. Tam and Piero Migliorato,
        \n“Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Polycrystalline Silicon Thin-Film Transistors”
        \nJpn. J. Appl. Phys. 40 (2001) pp. 5227-5236<\/p>\n

        Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda and Tsukasa Eguchi,
        \n“Dependence of Polycrystalline Silicon Thin-Film Transistor Characteristics on the Grain Boundary Location”
        \nJ. Appl. Phys., Vol. 89, No. 1, pp. 596 600, Jan. 2001<\/p>\n

        C. A. Dimitriadis, M. Kimura, M. Miyasaka, S. Inoue, F. V. Farmakis, J. Brini and G. Kamarinos,
        \n“Effect of grain boundaries on hot-carrier induced degradation in large grain polysilicon thin-film transistors”
        \nSolid-State Electronics, Vol. 44, Issue 11, 1 November 2000, pp. 2045-2051<\/p>\n

        Shih-Chung Lee and M. J. Lee,
        \n“Effects of multi-energetic grain-boundary trapping states on the electrical characteristics of poly-CdSe thin film transistors”
        \nJournal of Applied Physics, Vol. 88, No. 4, pp. 1999-2004, 15 August 2000<\/p>\n

        Mutsumi Kimura, Satoshi Inoue and Tatsuya Shimoda,
        \n“Device Simulation of Grain Boundaries and MOS Interface Roughness in Laser-Crystallized Poly-Si TFTs”
        \nDig. AM-LCD 2000, pp. 189-190, Jul. 2000<\/p>\n

        Mutsumi Kimura, Seiichiro Higashi and Toshiyuki Sameshima,
        \n“Device Simulation of Grain Boundaries in Poly-Si Films”
        \nTechnical Report of IEICE, ED2000-11, pp. 9-14, April 2000 [in Japanese]<\/p>\n

        Mutsumi Kimura, Seiichiro Higashi and Toshiyuki Sameshima,
        \n“Device Simulation of Grain Boundaries in Polysilicon films”
        \nExt. Abstr. (47th Spring Meet. 2000); Japan Society of Applied Physics and Related Societies, No. 2<\/p>\n

        Mutsumi Kimura, Tsukasa Eguchi, Satoshi Inoue and Tatsuya Shimoda,
        \n“Device Simulation of Grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors”
        \nJpn. J. Appl. Phys. Vol. 39 (2000) pp. L775-L778<\/p>\n

        J. S. Yoo et al.,
        \n“Reliability of low temperature poly-Si TFT employing counter-doped lateral body terminal”
        \nProc. IEDM 2000, pp. 217-220.<\/p>\n

        Mutsumi Kimura and Satoshi Inoue,
        \n“Device Simulation of Interface Roughness in Laser-Crystallized p-Si TFTs”
        \nDig. AM-LCD \u00b499, pp. 263-266, Jul. 1999<\/p>\n

        F. V. Farmakis, C. A. Dimitriadis, J. Brini, G. Kamarinos, V. K. Gueorguiev and Tz. E. Ivanov,
        \n“Hot-carrier phenomena in high temperature processed undoped-hydrogenated n-channel polysilicon thin film transistors (TFTs)”
        \nSolid-State Electronics, Vol. 43, Issue 7, July 1999, pp. 1259-1266<\/p>\n

        M. J. Lee and Shih-Chung Lee,
        \n“Extraction of the trap density and mobility in poly-CdSe thin films”
        \nSolid-State Electronics, Vol. 43, Issue 4, April 1999, pp. 833-838<\/p>\n

        G. A. Armstrong, J. R. Ayres and S. D. Brotherton,
        \n“Numerical simulation of transient emission from deep level traps in polysilicon thin film transistors”
        \nSolid-State Electronics, Vol. 41, Issue 6, June 1997, pp. 835-844<\/p>\n

        Armstrong, G. A., Brotherton S. D. and Ayres, J. R.,
        \n“Simulation of transient emission in polysilicon thin film transistors”
        \nSolid State Electronics, 40, 1997, pp 835-844<\/p>\n

        Armstrong, G. A. and Uppal S.,
        \n“Modelling of laser annealed polysilicon thin film transistor characteristics”
        \nIEEE Transactions Electron Device Letters, Vol. 18, Issue 7, July 1997, pp 315-318<\/p>\n

        Uppal S. and Armstrong G. A.,
        \n“Differentiation of grain and grain boundary effects in polysilicon thin film transistors”
        \nProc SSDM, Hamamatsu, Japan, 1997, pp. 356-357<\/p>\n

        Armstrong, G. A. Brotherton S. D. and Ayres, J. R.,
        \n“A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors”
        \nSolid State Electronics, Vol. 39, Issue 9, September 1996, pp. 1337-1346<\/p>\n<\/div><\/section><\/div>

        <\/div>